Sharing memory pages and page tables among computer processes

• US 6,085,296 A
• Filed: 11/12/1997
• Issued: 07/04/2000
• Est. Priority Date: 11/12/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company), Victor Levada
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Noel, Karen Lee, Karkhanis, Nitin Y.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/968,238
• Time in Patent Office: 965 Days
• Field of Search: 711/206, 711/207, 711/208, 711/209, 711/147, 711/148, 711/150, 711/151, 711/152, 711/153, 711/163
• US Class Current: 711/147
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures

Abstract

A method of managing computer memory pages. The sharing of a program-accessible page between two processes is managed by a predefined mechanism of a memory manager. The sharing of a page table page between the processes is managed by the same predefined mechanism. The data structures used by the mechanism are equally applicable to sharing program-accessible pages or page table pages.

Claims

1. A system for sharing computer memory, comprising:

a first data structure in the memory describing one or more pages of physical memory, said pages of physical memory containing data shared by a plurality of processes; and

a second data structure in the memory describing a set of shared page table pages, said shared page table pages mapping said pages of physical memory to address spaces of said processes;

wherein each of said first and second data structures comprises a respective global section descriptor (GSD) and global section table entry (GSTE), the respective GSD describing a global section and including a handle name for managing the section, a first field containing an index into a global section table and identifying the respective GSTE, and security-related information, the respective GSTE containing a pointer to the respective GSD, and a count of a number of pages in the global section.

2. The system of claim 1, wherein said page table pages are hierarchically arranged in a multi-level tree, and further comprising a third data structure describing a set of shared page table pages at a level of said tree different than the level of the page table pages described by said second data structure.

3. The system of claim 1, wherein said shared page table pages are mapped into address spaces of said plurality of processes.

4. The system of claim 1, wherein a process from among said plurality uses a single name to refer collectively to said first and second data structures in a system service request.

5. The system of claim 4, wherein said single name is stored in said first data structure.

6. The system of claim 1, wherein each of the first and second data structures are instantiated as a pair of corresponding subsidiary data structures, each member of each pair including a reference for locating the other member of the pair.

7. The system of claim 1, further comprising a memory management process for moving the contents of said shared page table entries and the contents of said shared data pages between memory and secondary memory.

8. The system of claim 7 wherein said secondary memory is a disk drive.

9. A computer memory, comprising:

a program-accessible page stored in the memory, being shared among two processes in a computer system;

a translation page stored in the memory, describing a virtual-to-physical address mapping for memory references, the translation page being shared among the two processes; and

a memory manager for managing the program-accessible page and the translation page, and for managing the sharing among the processes of the program-accessible page and the translation page, the memory manager comprising a global section descriptor (GSD) and a global section table entry (GSTE), the GSD describing a global section and including a handle name for managing the section, a first field containing an index into a global section table and identifying the GSTE, and security-related information, the GSTE containing a pointer to the GSD, and a count of a number of pages in the global section.

10. The computer memory of claim 9, the translation page thereof being a first translation page, further comprising:

a second translation page stored in the memory, describing an address translation for a part of a virtual address, an entry in the second translation page pointing to the first translation page, the second translation page being shared among the two processes, the sharing being managed by the memory manager.

11. The computer memory of claim 10, wherein:

the memory manager pages the first translation page between a primary and secondary level of the memory.

12. The computer memory of claim 10, wherein:

the memory manager locks the first translation page into the primary level of the memory.

13. The computer memory of claim 9, wherein the memory manager keeps the program-accessible page locked into a primary level of the memory.

14. The computer memory of claim 9, wherein the memory manager pages the program-accessible page between a primary and a secondary level of the memory.

15. The computer memory of claim 14, wherein:

the memory manager enforces a discipline in which the highest-level translation page shared among the processes is locked into the primary level of the memory.

16. A method of managing computer memory pages, comprising the steps of:

managing sharing of a program-accessible page between two processes, under control of a single predefined mechanism of a memory manager; and

managing sharing of a translation page between the processes also under control of the single predefined mechanism, the translation page describing a virtual-to-physical address mapping;

wherein the memory manager uses a global section descriptor (GSD) and a global section table entry (GSTE), the GSD describing a global section and including a handle name for managing the section, a first field containing an index into a global section table and identifying the GSTE, and security-related information, the GSTE containing a pointer to the GSD, and a count of a number of pages in the global section.

17. The method of claim 16, wherein:

the program-accessible page is allocated by a non-privileged process from a pool of memory reserved out of the system page pool and designated as non-pageable.

18. The method of claim 17, wherein:

the program-accessible page is a page from among a pool reserved for allocation as a contiguous group of physical pages.

19. The method of claim 17, wherein:

the program-accessible page is a page from among a pool reserved for allocation on page fault.

20. The method of claim 16, further comprising the step of:

enforcing an address alignment of the program-accessible page.

21. The method of claim 20, wherein the enforced alignment is determined based on a requested length of the program-accessible page.

22. The method of claim 21, wherein the requested length is rounded up to a multiple of a length of a memory structure larger than a page.

23. The method of claim 20, further comprising the step of:

encoding in a single entry in the translation page a mapping corresponding to multiple entries of the page.

24. The method of claim 20, further comprising the step of:

allocating a process-private translation page for the program-accessible page if the process violates the enforced address alignment.

25. The method of claim 16, further comprising the step of:

attributing to a region of virtual memory a property that memory objects mapped into the region will be mapped with shared translation pages.

26. The method of claim 25, further comprising the step of:

enforcing a security constraint on the region, in which private memory objects are excluded from being mapped using the shared translation page.

27. The method of claim 26, further comprising the step of:

enforcing the security constraint based on a range of virtual addresses with a start address and a length determined by the amount of address space mapped by a translation page.

28. A computer, comprising:

a first data structure in a memory of the computer for managing the sharing of a leaf page of physical memory among a plurality of processes; and

a second data structure in the memory of the computer for managing the sharing of a page table page among said processes, said shared page table page mapping virtual addresses to said leaf page;

wherein said first and second data structures comprise a global section descriptor (GSD) and a global section table entry (GSTE), the GSD describing a global section and including a handle name for managing the section, a first field containing an index into a global section table and identifying the GSTE, and security-related information, the GSTE containing a pointer to the GSD, and a count of a number of pages in the global section.

29. The computer of claim 28, wherein said plurality of processes use a single name to request system services involving said first and second data structures.

30. The computer of claim 29, wherein:

the first and second data structures are created responsive to a single entry in a memory reservation request.

31. The computer of claim 30, wherein:

a size of a page table section embracing the page table page is determined from a requested size for an allocation embracing the leaf page.

32. The computer of claim 29, wherein the single name is stored in said first data structure.

33. The computer of claim 28, wherein:

the memory manager pages the first translation page between a primary and secondary level of the memory.

34. The computer of claim 28, wherein:

the memory manager enforces a discipline in which the highest-level translation page shared among the processes is locked into the primary level of the memory.

35. The computer of claim 28, wherein:

the memory manager locks the first translation page into the primary level of the memory.

36. The computer of claim 28, wherein the memory manager pages the program-accessible page between a primary and a secondary level of the memory.

37. The computer of claim 28, wherein:

the program-accessible page is allocated by a non-privileged process from a pool of memory reserved out of the system page pool and designated as non-pageable.

38. The computer of claim 28, wherein:

the program-accessible page is a page from among a pool reserved for allocation as a contiguous group of physical pages.

39. The computer of claim 28, wherein:

a process-private translation page for the program-accessible page is allocated if the process violates an enforced address alignment.

40. The computer of claim 28, wherein:

a decision to map the leaf page with the shared page table page was determined according to an attribute of a region of virtual memory.

41. The computer of claim 28, wherein:

a security constraint on the region is enforced, in which private memory objects cannot be mapped using the shared translation page.

42. The computer of claim 41, wherein:

the security constraint is enforced based on a range of virtual addresses with a start address and a length determined by the amount of address space mapped by a translation page.