Central processing unit including APX and DSP cores and including selectable APX and DSP execution modes

• US 6,085,314 A
• Filed: 11/14/1997
• Issued: 07/04/2000
• Est. Priority Date: 03/18/1996
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mills, Andrew, Asghar, Saf
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/969,858
• Time in Patent Office: 963 Days
• Field of Search: 395/800.23, 395/800.35, 395/383, 395/387, 395/359, 395/800.75, 712/23, 712/35, 712/204, 712/206, 712/213, 712/207, 712/203, 712/208, 712/210, 712/211, 712/217, 712/230, 712/245
• US Class Current: 712/213
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.

Claims

1. A central processing unit which performs general purpose processing functions and digital signal processing (DSP) functions, comprising:

an instruction memory for storing a plurality of instructions, wherein said instruction memory stores one or more sequences of instructions which are intended to perform a DSP function;

a processor mode memory for storing one or more processor mode bits, wherein said one or more processor mode bits indicate whether a sequence of instructions implements a DSP function;

a function preprocessor coupled to the instruction memory and coupled to the processor mode memory, wherein the function preprocessor is operable to examine said one or more processor mode bits in said processor mode memory to determine whether a sequence of said instructions in said instruction memory is intended to perform a digital signal processing function, wherein the function preprocessor is operable to convert said sequence of said instructions in said instruction memory into a DSP function identifier if said one or more processor mode bits in said processor mode memory indicate that said sequence of said instructions in said instruction memory is intended to perform a DSP function;

at least one general purpose processing core coupled to the function preprocessor for executing instructions in said instruction memory, wherein the function preprocessor provides a sequence of instructions to said at least one general purpose processing core if said one or more processor mode bits indicate that said sequence of said instructions in said instruction memory is not intended to perform a DSP function;

at least one digital signal processing core coupled to the function preprocessor for performing digital signal processing functions, wherein the function preprocessor is operable to provide said digital signal processing function identifier to said at least one digital signal processing core, wherein the at least one digital signal processing core receives said digital signal processing function identifier and performs a digital signal processing function in response to said received digital signal processing function identifier from said function preprocessor.

2. The central processing unit of claim 1, wherein said instruction memory stores a first sequence of instructions which does not perform a digital signal processing function, and wherein said instruction memory stores a second sequence of instructions which performs a digital signal processing function;

wherein said at least one general purpose processing core executes said first sequence of instructions;

wherein said at least one digital signal processing core performs said digital signal processing function in response to said received digital signal processing function identifier, wherein said digital signal processing function performed by said digital signal processing core is substantially equivalent to execution of said second sequence of instructions.

3. The central processing unit of claim 1, wherein said processor mode memory stores a respective value for said one or more processor mode bits for each respective sequence of instructions in said instruction memory;

wherein said respective value indicates whether said respective sequence of instructions implements a DSP function.

4. The central processing unit of claim 1, wherein said processor mode memory stores a value indicating a type of DSP function implemented by a sequence of instructions;

wherein said processor mode memory stores said value indicating said type of DSP function implemented by said sequence of instructions when said one or more processor mode bits indicate that said sequence of instructions implements a DSP function;

wherein said function preprocessor uses said value indicating said type of DSP function implemented by said sequence of instructions in converting said sequence of said instructions in said instruction memory into a DSP function identifier.

5. The central processing unit of claim 1, wherein said at least one digital signal processing core provides data and timing signals to said at least one general purpose processing core.

6. The central processing unit of claim 1, wherein said function preprocessor generates a digital signal processing function identifier and one or more parameters in response to said one or more processor mode bits indicating that said sequence of instructions in said instruction memory is intended to perform a digital signal processing function.

7. The central processing unit of claim 1, wherein said at least one general purpose processing core is compatible with the X86 family of microprocessors.

8. The central processing unit of claim 7, wherein said plurality of instructions are X86 opcodes.

9. The central processing unit of claim 1, wherein said at least one digital signal processing core is adapted for performing one or more mathematical operations from the group consisting of convolution, correlation, Fast Fourier Transforms, and inner product.

10. The central processing unit of claim 1, wherein said at least one general purpose processing core and said at least one digital signal processing core operate substantially in parallel.

19. The method of claim 9, wherein said general purpose central processing unit core is compatible with the X86 family of microprocessors;

wherein said one or more sequences of instructions comprise X86 opcodes.

11. A method for executing instructions in a central processing unit (CPU), wherein the CPU includes at least one general purpose CPU core and at least one digital signal processing (DSP) core, the method comprising:

storing one or more sequences of instructions in an instruction memory for execution by the central processing unit;

storing one or more processor mode bits in a processor mode memory, wherein said one or more processor mode bits indicate whether a sequence of instructions implements a DSP function;

examining a sequence of instructions in said instruction memory;

examining said one or more processor mode bits to determine whether said sequence of instructions in said instruction memory is intended to perform a DSP function;

converting said sequence of instructions in said instruction memory into a DSP function identifier if said one or more processor mode bits indicate that said sequence of instructions in said instruction memory is intended to perform a DSP function;

the digital signal processing core receiving said DSP function identifier;

the digital signal processing core performing a digital signal processing function in response to said received digital signal processing function identifier.

12. The method of claim 11, further comprising:

said general purpose central processing unit core executing said sequence of instructions if said one or more processor mode bits indicate that said sequence of instructions in said instruction memory is not intended to perform a DSP function.

13. The method of claim 12, further comprising:

wherein said storing comprises storing a first sequence of instructions in said instruction memory which performs a first digital signal processing function;

wherein said storing comprises storing a second sequence of instructions in said instruction memory which does not perform a digital signal processing function;

wherein said converting converts said first sequence of instructions in said instruction memory which is intended to perform said first digital signal processing function into a first digital signal processing function identifier;

wherein said performing comprises said digital signal processing core performing said first digital signal processing function in response to said first digital signal processing function identifier, wherein said performing said first digital signal processing function is substantially equivalent to execution of said first sequence of instructions; and

said general purpose central processing unit core executing said second sequence of instructions.

14. The method of claim 11, wherein said storing one or more processor mode bits in the processor mode memory comprises storing a respective value for said one or more processor mode bits for each respective sequence of instructions in said instruction memory;

wherein said respective value indicates whether said respective sequence of instructions implements a DSP function.

15. The method of claim 11, further comprising:

storing a value in said processor mode memory indicating a type of DSP function implemented by a sequence of instructions;

wherein said processor mode memory stores said value indicating said type of DSP function implemented by said sequence of instructions when said one or more processor mode bits indicate that said sequence of instructions implements a DSP function;

wherein said function preprocessor uses said value indicating said type of DSP function implemented by said sequence of instructions in converting said sequence of said instructions in said instruction memory into a DSP function identifier.

16. The method of claim 11, further comprising:

said digital signal processing core and said general purpose central processing unit core operating substantially in parallel.

17. The method of claim 11, further comprising:

said digital signal processing core providing data and timing signals to said general purpose central processing unit core.

18. The method of claim 11, further comprising:

said function preprocessor generating a digital signal processing function identifier and one or more parameters in response to said determining that said sequence of instructions in said instruction memory is intended to perform a digital signal processing function.

20. The method of claim 11, wherein said digital signal processing core performs one or more mathematical operations from the group consisting of convolution, correlation, Fast Fourier Transform, and inner product.