Electronic system having a chip integrated power-on reset circuit with glitch sensor

• US 6,085,342 A
• Filed: 05/06/1997
• Issued: 07/04/2000
• Est. Priority Date: 05/06/1997
• Status: Expired due to Term

• Current Assignee: Blackberry Limited
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Marholev, Bojko, Bjork, Christian, Gardenfors, Torbjorn
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/851,875
• Time in Patent Office: 1,155 Days
• Field of Search: 714/724, 714/733, 714/734, 714/736, 714/738, 714/745, 395/750, 327/143
• US Class Current: 714/724
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A power-on reset circuit with glitch sensing capabilities is formed as part of the same integrated circuit chip containing other logical circuits. A port included in the integrated circuit chip enables a power-on reset signal generated by the integrated power-on reset circuit to be output from the chip and applied to other chips installed in a single chip or multi-chip electronic system. The power-on reset circuit compares a capacitor stored reset voltage to a reference voltage and outputs the power-on reset signal when the reset voltage falls below the reference voltage. Storage of the reset voltage by the capacitor is controlled by a glitch sensor which detects changes in voltage provided by a power supply in excess of a given threshold and, in response thereto, triggers a capacitor discharge. This causes the reset voltage to fall below the reference voltage, and the power-on reset signal to be output. Furthermore, for synchronously operated systems, the output power-on reset signal is synchronized with an edge of an output clock signal.

Claims

1. A multi-chip electronic system implementing a certain functionality, comprising:

a plurality of integrated circuit chips, each including resettable logic components implementing a certain sub-functionality in furtherance of the certain functionality;

a power-on reset circuit integrated within a certain one of the plurality of integrated circuit chips, the power-on reset circuit generating a power-on reset signal responsive to a power supply change, power-up, or glitch;

an output port on the certain one of the plurality of integrated circuit chips, the output port connected to receive the generated power-on reset signal; and

a connection from the output port on the certain one of the plurality of integrated circuit chips to the resettable logic on the others of the plurality of integrated circuit chips for application thereto of the generated power-on reset signal.

2. The system of claim 1 further including means for interconnecting between the resettable logic components of the plurality of integrated circuit chips.

3. The system of claim 1 wherein the power-on reset circuit comprises:

means for generating a reference voltage;

means for storing a reset voltage;

means for sensing the power supply change, power-up, or glitch and in response thereto discharging the stored reset voltage; and

means for comparing the reference voltage to the reset voltage and generating the power-on reset signal if the reset voltage is discharged and falls below the reference voltage.

4. The system of claim 3 wherein the means for storing comprises:

a capacitor; and

a current source for charging the capacitor to the reset voltage.

5. The system of claim 3 wherein the means for comparing comprises an operational amplifier configured as a comparator and having a first input receiving the reset voltage and a second input receiving the reference voltage.

6. The system of claim 3 wherein the means for sensing and discharging comprises:

means for storing a glitch voltage;

means for measuring a difference between the stored glitch voltage and power supply voltage, and comparing the measured difference to a threshold; and

switch means connected between the means for storing the reset voltage and ground for discharging the stored reset voltage to ground if the measured difference exceeds the threshold.

7. The system of claim 3 wherein the means for sensing and discharging comprises:

a capacitor;

means for charging the capacitor with a glitch voltage;

a first transistor connected between the capacitor and a power supply, and operable to compare a power supply voltage and the glitch voltage to detect the power supply change, power-up, or glitch; and

a second transistor connected between the first transistor, the means for storing the reset voltage and a ground, and operable to discharge the stored reset voltage to ground in response to a first transistor detected power supply change, power-up, or glitch.

8. The system of claim 7 wherein the power-on reset circuit further comprises a third transistor connected between the first transistor, second transistor, ground and a voltage reference.

9. The system of claim 1 further including:

a clock generator integrated within the certain one of the plurality of integrated circuit chips, the clock generator generating a clock signal having an edge;

a clock port on the certain one of the plurality of integrated circuit chips, the clock port connected to receive the generated clock signal; and

a synchronization circuit integrated within the certain one of the plurality of integrated circuit chips and connected to the power-on reset circuit and the clock generator, the synchronization circuit operating to synchronize an edge of the power-on reset signal output from the output port with the edge of the clock signal output from the clock port.

10. A reset circuit, comprising:

means for generating a reference voltage;

means for storing a reset voltage;

means for storing a glitch voltage;

means for measuring a difference between the stored glitch voltage and power supply voltage, and comparing the measured difference to a threshold;

switch means connected between the means for storing the reset voltage and around for discharging the stored reset voltage to ground it the measured difference exceeds the threshold; and

means for comparing the reference voltage to the reset voltage and generating a reset signal if the reset voltage is discharged and falls below the reference voltage.

11. The circuit as in claim 10 wherein the means for storing a reset voltage comprises:

a capacitor; and

a current source for charging the capacitor to the reset voltage.

12. The circuit as in claim 10 wherein the means for comparing comprises an operational amplifier configured as a comparator and having a first input receiving the reset voltage and a second input receiving the reference voltage.

13. The circuit of claim 10 wherein the means for storing a glitch voltage comprises a capacitor;

and the means for measuring a difference comprises a first transistor connected between the capacitor and a power supply, and operable to compare a power supply voltage and the glitch voltage to detect the power supply glitch; and

the switch means comprises a second transistor connected between the first transistor, the means for storing the reset voltage and a ground, and operable to discharge the stored reset voltage to ground in response to a first transistor detected power supply glitch.

14. An integrated circuit chip implementing a certain functionality, comprising:

a plurality of resettable logic components integrated within the circuit chip and implementing a certain sub-functionality in furtherance of the certain functionality;

a power-on reset circuit integrated within the circuit chip, the power-on reset circuit generating a power-on reset signal responsive to a power supply change, power-up, or glitch; and

means for applying the generated power-on reset signal to each of the logic components.

15. The system of claim 14 wherein the power-on reset circuit comprises:

means for generating a reference voltage;

means for storing a reset voltage;

means for sensing the power supply change, power-up, or glitch and in response thereto discharging the stored reset voltage; and

means for comparing the reference voltage to the reset voltage and generating the power-on reset signal if the reset voltage is discharged and falls below the reference voltage.

16. The system of claim 15 wherein the means for storing comprises:

a capacitor; and

a current source for charging the capacitor to the reset voltage.

17. The system of claim 15 wherein the means for comparing comprises an operational amplifier configured as a comparator and having a first input receiving the reset voltage and a second input receiving the reference voltage.

18. The system of claim 15 wherein the means for sensing and discharging comprises:

means for storing a glitch voltage;

means for measuring a difference between the stored glitch voltage and power supply voltage, and comparing the measured difference to a threshold; and

switch means connected between the means for storing the reset voltage and ground for discharging the stored reset voltage to ground if the measured difference exceeds the threshold.

19. The system of claim 15 wherein the means for sensing and discharging comprises:

a capacitor;

means for charging the capacitor with a glitch voltage;

a first transistor connected between the capacitor and a power supply, and operable to compare a power supply voltage and the glitch voltage to detect the power supply change, power-up, or glitch; and

a second transistor connected between the first transistor, the means for storing the reset voltage and a ground, and operable to discharge the stored reset voltage to ground in response to a first transistor detected power supply change, power-up, or glitch.

20. The system of claim 19 wherein the power-on reset circuit further comprises a third transistor connected between the first transistor, second transistor, ground and a voltage reference.

21. The system of claim 14 further including:

a clock generator integrated within the circuit chip, the clock generator generating a clock signal having an edge; and

a synchronization circuit integrated within the circuit chip and connected to the power-on reset circuit and the clock generator, the synchronization circuit operating to synchronize an edge of the power-on reset signal for application to the logic components with the edge of the clock signal.

22. A method for generating a reset signal, comprising;

storing a reset voltage;

storing a glitch voltage;

comparing a lower supply voltage to the glitch voltage;

generating a switching signal if the comparison indicates that the supply voltage differs from the glitch voltage by more that a predetermined threshold;

discharging the stored reset voltage in response to the detection of the power supply change or power-up, or generation of switching signal;

comparing the stored reset voltage to a reference voltage; and

outputting the reset signal if the comparison indicates that the stored reset voltage has dropped below the reference voltage.