Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers

• US 6,086,629 A
• Filed: 12/04/1997
• Issued: 07/11/2000
• Est. Priority Date: 12/04/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Tran, Jennifer T., Goetting, F. Erich, McGettigan, Edward S.
• Primary Examiner(s): Weinhardt, Robert A.
• Assistant Examiner(s): Joyce, Margaret M.
• Application Number:
  US08/985,301
• Time in Patent Office: 950 Days
• Field of Search: 395/500.02, 395/500.13, 395/500.17, 395/500.03, 395/500.08, 395/500.09, 395/500.11
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of computer aided design of coarse grain FPGA'"'"'s by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a "local output" (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers. They'"'"'re referred to as virtual buffers because they serve only a design function and do not actually exist in a CLB. The virtual buffers provide placement directives such as to connect a primitive cell output to another CLB input within some prescribed geographical limit such as within 4 or 6 CLBs of the one in which the buffer is "located".

Claims

1. A method of designing interconnections in a field programmable gate array (FPGA) of the type having a plurality of configurable logic blocks, each such configurable logic block having a plurality of primitive cells, each such primitive cell having at least one input and at least one output;

the method comprising the following steps;

a) establishing a library of primitive cells;

b) defining which primitive cell outputs may be connected to respective primitive cell inputs;

c) defining a set of connection classes;

d) determining which connection classes are attributed to the inputs and outputs of primitive cells in said library; and

e) deriving timing and power parameters for the primitive cells in said library;

wherein steps a) to e) are performed prior to placement and routing in said FPGA.

2. The method recited in claim 1 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell to an input of another primitive cell within the same logic block.

3. The method recited in claim 1 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within one logic block to an input of another primitive cell within another logic block.

4. The method recited in claim 1 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within one logic block to an input of another primitive cell within another logic block which is within a preselected number of logic blocks distance from said one logic block.

5. The method recited in claim 1 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within a first logic block to an input of another primitive cell within a second logic block located within the same row or column as said first logic block.

6. The method recited in claim 1 further comprising the step of:

f) designating some primitive cell outputs as local outputs for connection to primitive cell inputs only within the same logic block.

7. The method recited in claim 1 further comprising the step of:

f) designating some primitive cell outputs as local outputs for connection to primitive cell inputs of virtual buffers.

15. The method recited in claim 1 further comprising the step of:

f) defining a virtual connection buffer designed for providing a fast feedback path between an output and an input of a configurable logic block.

8. A method of designing interconnections in a field programmable gate array (FPGA) of the type having a plurality of input/output blocks, each such input/output block having a plurality of primitive cells, each such primitive cell having at least one input and at least one output;

the method comprising the following steps;

a) establishing a library of primitive cells;

b) defining which primitive cell outputs may be connected to respective primitive cell inputs;

c) defining a set of connection classes;

d) determining which connection classes are attributed to the inputs and outputs of primitive cells in said library; and

e) deriving timing and power parameters for the primitive cells in said library;

wherein steps a) to e) are performed prior to placement and routing in said FPGA.

9. The method recited in claim 8 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell to an input of another primitive cell within the same input/output block.

10. The method recited in claim 8 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within one input/output block to an input of another primitive cell within another input/output block.

11. The method recited in claim 8 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within one input/output block to an input of another primitive cell within another input/output block which is within a preselected number of input/output blocks distance from said one input/output block.

12. The method recited in claim 8 further comprising the step of:

f) designating some primitive cell outputs as local outputs for connection to primitive cell inputs only within the same input/output block.

13. The method recited in claim 8 further comprising the step of:

f) defining a virtual connection buffer designated for connecting an output of a primitive cell within one input/output block to an input of another primitive cell within another input/output block which is within a preselected number of input/output blocks distance from said one input/output block.

16. The method recited in claim 8 further comprising the step of:

f) defining a virtual connection buffer designed for providing a fast feedback path between an output and an input of a configurable logic block.

14. In a field programmable gate array (FPGA) of the type having a plurality of configurable logic blocks, each such configurable logic block having a plurality of primitive cells, each such primitive cell having at least one input and at least one output, said configurable logic blocks being arranged in logic block groups, said logic blocks being interconnectable by local lines within one of said logic block groups and by long lines extending between said logic block groups;

a method of evaluating a user'"'"'s design for placement into said configurable logic blocks comprising the following steps;

a) establishing a library of said primitive cells, including library elements representing said primitive cells and virtual buffers representing selected ones of said lines;

b) defining which primitive cell outputs may be connected to respective primitive cell inputs;

c) defining a set of connection classes;

d) determining which connection classes are attributed to the inputs and outputs of primitive cells and virtual buffers in said library; and

e) deriving timing and power parameters for the primitive cells and virtual buffers in said library;

wherein steps a) to e) are performed prior to placement and routing in said FPGA.