Test structure for monitoring overetching of silicide during contact opening

• US 6,087,189 A
• Filed: 04/24/1997
• Issued: 07/11/2000
• Est. Priority Date: 04/24/1997
• Status: Expired due to Term

• Current Assignee: National Science Council
• Original Assignee: National Science Council
• Inventors: Huang, Tiao-Yuan
• Primary Examiner(s): Powell, William A.
• Assistant Examiner(s): GOUDREAU, GEORGE A
• Application Number:
  US08/847,513
• Time in Patent Office: 1,174 Days
• Field of Search: 438/10, 438/11, 438/12, 438/13, 438/721, 422/10
• US Class Current: 438/10
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

For the contact opening in advanced IC processing, it becomes critical to monitor the degree of overetching of the thin silicide layer and also to obtain the etching rate of the silicide layer. A method is disclosed which will allow the electrical measurements of the sheet resistance of the exposed (by the contact etch) silicide layer, thus allowing electrical measurements to the integrity as well as the thickness of the remaining silicide layer. A main feature of the disclosed test method is a modification of the conventional van der Pauw test structure, or of the cross-bridge structure (which will allow electrical measurement of the line width, in addition to the sheet resistance information). Contrary to the conventional van der Pauw structure or cross-bridge structure where the contact opening pattern is designed to expose only the specific areas needed for allowing electrical connection to the four measurement pads, the contact opening mask is designed to expose some or all of the van der Pauw or cross-bridge structure, thus allowing the electrical measurement of the degree of silicide overetching during contact opening. The disclosed test method and corresponding structure can be applied as an on-wafer process monitor tool following the complete normal process flow, thus serving as a convenient on-wafer monitor.

Claims

1. A method of measuring a degree of overetching of a silicide layer on a semiconductor wafer, comprising:

forming a van der Pauw or cross-bridge structure on the wafer;

forming a silicide layer over the van der Pauw or cross-bridge structure;

subjecting the silicide layer over the van der Pauw or cross-bridge structure to a photolithographic etching process, which process includes masking a photoresist layer on the silicide layer such that, when the photoresist layer is etched in the lithographic process, the silicide layer over at least a portion of the center of the van der Pauw or cross-bridge structure is etched; and

measuring the electrical characteristics of the van der Pauw or cross-bridge structure to determine a degree of overetching of a silicide layer.

2. A method of measuring a degree of overetching of a silicide layer as recited in claim 1, wherein the photolithographic etching process includes masking a photoresist layer on the silicide layer such that, when the photoresist layer is etched in the lithographic process, the silicide layer over the entire van der Pauw or cross-bridge structure is etched.

3. A method of measuring a degree of overetching of a silicide layer as recited in claim 1, wherein the van der Pauw or cross-bridge structure is formed in the semiconductor wafer by a diffusion layer or a polygate layer.