Method for fabricating a very dense chip package

• US 6,087,199 A
• Filed: 02/04/1998
• Issued: 07/11/2000
• Est. Priority Date: 02/04/1998
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Greschner, Johann, Davari, Bijan, Pogge, H. Bernhard, Kalter, Howard L.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): JONES, JOSETTA I
• Application Number:
  US09/018,737
• Time in Patent Office: 888 Days
• Field of Search: 438/110, 438/106
• US Class Current: 438/106
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15157 : Top view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 μm. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 μm<G≦100 μm. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Claims

1. A method, comprising:

providing a carrier substrate including a plurality of surface projections having sloping sidewalls;

providing a plurality of chips having bottom faces forming surface depressions with beveled edges matching and being in conformal juxtaposition with the sloping sidewalls, the plurality of chips also forming top faces at sides opposite the bottom faces, portions of at least two of the top faces lying substantially in at least two planes separated by a minimum distance (D) in a range of 0.0 μ

m<

D≦

2 μ

m, at least two of the chips being separated by a gap (G) having a minimum spacing in a range of 1 μ

m<

G≦

100 μ

m, and

providing at least one metallic interconnect disposed over the portions and the gap.

2. The method as claimed in claim 1, wherein said step of providing at least one metallic interconnect includes providing a metallic interconnect having a width W over the top surfaces in a range only of 0.5 μ

m≦

W≦

5 μ

m.

3. The method as claimed in claim 1, wherein said step of providing at least one metallic interconnect includes providing a metallic interconnect having a width W in a range only of 1 μ

m≦

W≦

10 μ

m over the gap G.

4. The method as claimed in claim 1, wherein said distance D and said gap G are related according to the following relationship:

##EQU3##

5. The method as claimed in claim 1, wherein the metallic interconnect has a width over said gap greater than a width over at least one of said portions.

6. The method as claimed in claim 1, wherein the at least two chips have different primary electronic functions.

7. The method as claimed in claim 6, wherein the different primary functions are the functions of a microprocessor and a main memory.

8. The method as claimed in claim 1, wherein the at least two chips have identical primary electronic functions.

9. The method of claim 1, wherein said step of providing at least one metallic interconnect includes utilizing a hard mask arranged and dimensioned for the metallic interconnect.

10. The method of claim 1, wherein the carrier substrate includes an upper face comprised of a planar base surface portion bordering at least one of said projections, the projection has a flat top surface, the sloping sidewall of the projection extends from the planar base surface portion to the flat top surface of the projection, and one of the circuit chips includes a bottom face comprised of a planar outer chip surface portion bordering the surface depression and the surface depression has a planar recess bottom surface, and wherein the beveled edge of the surface depression extends from the bottom face to a planar recess bottom surface.

11. The method of claim 10, wherein the recess bottom surface rests on a flat top surface of the projection, and the bottom face rests on a planar base surface portion of the carrier substrate.

12. The method of claim 1, wherein the surface depression in at least one of the chips has at least two beveled edges and at least one of the carrier substrate projections has at least two sloping sidewalls, and wherein the at least two beveled edges of the surface depression in the at least one chip are in juxtaposition with the at least two sloping sidewalls of the at least one substrate projection.

13. The method of claim 1, wherein the surface depression in at least one of the chips has four beveled edges and at least one of the substrate projections has four sloping sidewalls, and wherein the four beveled edges of the surface depression in the at least one chip are in juxtaposition with the four sloping sidewalls of the at least one carrier substrate projection.

14. The method of claim 1, wherein said step of providing a carrier substrate includes selecting a material of at least a bulk portion of the carrier substrate to have a same crystallographic structure as a material of at least a bulk portion of at least one of the chips.

15. The method of claim 14, wherein the material of the bulk portion of the carrier substrate is essentially the same as the material of the bulk portion of the at least one chip.

16. The method of claim 15, wherein the material is a semiconductor material.

17. The method of claim 16, wherein the material is silicon.

18. The method of claim 17, wherein the silicon is a (100) wafer, the bottom face is aligned with a [110 ] direction and the beveled edge is a (111) oriented crystal face, and the flat top surface of the projection is aligned with the [110 ] direction and the sloping sidewall is a (111) oriented crystal face.

19. The method of claim 17, wherein the sloping sidewall of the projection forms an angle of approximately 125.3°

with the flat top surface of the projection, and the beveled edge forms an angle of approximately 125.3°

with the bottoms face.

20. A method, comprising:

providing a carrier substrate, the carrier substrate comprising an upper face including planar outer surface portions bordering at least two neighboring surface recesses having sloping sidewalls and flat recess bottom surfaces, the at least two neighboring surface recesses being separated by a minimum spacing of greater than 1 μ

m;

providing at least two integrated circuit chips having different thicknesses, the at least two integrated circuit chips comprising top faces and bottom faces, the bottom faces including projections, the projections having planar outer surfaces and beveled edges matching the sloping sidewalls;

positioning the beveled edges and the sloping sidewalls to be in conformal juxtapositions, so that the chip projections are conformally located in the surface recesses of the carrier substrate, and that the top faces of the at least two chips lie substantially in respective planes separated by a minimum distance corresponding substantially to the difference between the different thicknesses, and

providing at least one metallic interconnect disposed over the top faces of the at least two chips.

21. The method as claimed in claim 20, wherein said step of providing at least one metallic interconnect includes utilizing a hard mask configured for the metallic interconnect.

22. The method as claimed in claim 20, wherein said step of providing the at least one metallic interconnect comprises providing the interconnect over the spacing between the at least two neighboring surface recesses.

23. The method as claimed in claim 22, wherein said step of providing the at least one metallic interconnect further comprises providing the interconnect such that the interconnect has a gradual slope over the spacing.