Method for fabricating a very dense chip package
First Claim
1. A method, comprising:
- providing a carrier substrate including a plurality of surface projections having sloping sidewalls;
providing a plurality of chips having bottom faces forming surface depressions with beveled edges matching and being in conformal juxtaposition with the sloping sidewalls, the plurality of chips also forming top faces at sides opposite the bottom faces, portions of at least two of the top faces lying substantially in at least two planes separated by a minimum distance (D) in a range of 0.0 μ
m<
D≦
2 μ
m, at least two of the chips being separated by a gap (G) having a minimum spacing in a range of 1 μ
m<
G≦
100 μ
m, andproviding at least one metallic interconnect disposed over the portions and the gap.
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Accused Products
Abstract
A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 μm. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 μm<G≦100 μm. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.
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Citations
23 Claims
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1. A method, comprising:
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providing a carrier substrate including a plurality of surface projections having sloping sidewalls; providing a plurality of chips having bottom faces forming surface depressions with beveled edges matching and being in conformal juxtaposition with the sloping sidewalls, the plurality of chips also forming top faces at sides opposite the bottom faces, portions of at least two of the top faces lying substantially in at least two planes separated by a minimum distance (D) in a range of 0.0 μ
m<
D≦
2 μ
m, at least two of the chips being separated by a gap (G) having a minimum spacing in a range of 1 μ
m<
G≦
100 μ
m, andproviding at least one metallic interconnect disposed over the portions and the gap. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method, comprising:
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providing a carrier substrate, the carrier substrate comprising an upper face including planar outer surface portions bordering at least two neighboring surface recesses having sloping sidewalls and flat recess bottom surfaces, the at least two neighboring surface recesses being separated by a minimum spacing of greater than 1 μ
m;providing at least two integrated circuit chips having different thicknesses, the at least two integrated circuit chips comprising top faces and bottom faces, the bottom faces including projections, the projections having planar outer surfaces and beveled edges matching the sloping sidewalls; positioning the beveled edges and the sloping sidewalls to be in conformal juxtapositions, so that the chip projections are conformally located in the surface recesses of the carrier substrate, and that the top faces of the at least two chips lie substantially in respective planes separated by a minimum distance corresponding substantially to the difference between the different thicknesses, and providing at least one metallic interconnect disposed over the top faces of the at least two chips. - View Dependent Claims (21, 22, 23)
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Specification