Method for increasing gate capacitance by using both high and low dielectric gate material

• US 6,087,208 A
• Filed: 03/31/1998
• Issued: 07/11/2000
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krishnan, Srinath, Yeap, Geoffrey Choh-Fei, Buynoski, Matthew, Krivokapic, Zoran
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): WHIPPLE, MATTHEW LAVERNE
• Application Number:
  US09/052,386
• Time in Patent Office: 833 Days
• Field of Search: 438/183, 438/264, 438/216, 438/287, 438/591, 438/285, 438/240
• US Class Current: 438/183
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.

Claims

1. A method for fabricating a MOSFET device including the step of:

forming a gate oxide including first and second gate oxide materials, the first gate oxide material having a dielectric constant of about ε

<

100 and the second gate oxide material having a dielectric constant of about ε

>

100 and a higher dielectric constant than the first gate oxide, the step of forming the gate oxide including the steps of;

forming the first gate oxide material over source/drain extension regions of the device;

etching a portion of the first gate oxide material between the source/drain extension regions of the device; and

replacing said etched portion by forming the second gate oxide material over a channel region of the device.

2. The method of claim 1, wherein the first gate oxide material has a thickness of about <

40 Å

.

3. The method of claim 1, wherein the second gate oxide material has about a thickness >

300 Å

.

4. The method of claim 1, wherein the first gate oxide material is selected from a group comprising:

SiO₂ and Si₃ N₄, and combinations thereof.

5. The method of claim 1, wherein the second gate oxide material is selected from a group comprising:

Al₂ O₃ ;

Ta₂ O₅ ;

TiO₂ ;

SrTiO₃ ;

ZnO;

PZT, and combinations thereof.

6. The method of claim 1 further including the step of forming a dummy gate.

7. The method of claim 6, wherein the dummy gate comprises nitride.

8. A method of fabricating a MOS transistor, comprising the steps of:

providing a substrate having isolating regions thereon;

forming a dummy gate structure over a portion of a first gate oxide material;

implanting indium into a n-well region;

implanting the well region to form lightly doped active regions;

forming spacers along sidewalls of the dummy gate;

implanting the well region to form source and drain regions;

etching the dummy gate;

etching a portion of the first gate oxide material that was under the dummy gate; and

forming a second gate oxide material over a channel region of the transistor.

9. The method of claim 8, wherein the first gate oxide material has a dielectric constant of about ε

<

100, has about a thickness <

40 Å

, and is selected from a group comprising;

SiO₂ and Si₃ N₄, and combinations thereof; and

wherein the second gate oxide material has a dielectric constant of about ε

>

100, has about a thickness >

300 Å

, and is selected from a group comprising;

Al₂ O₃ ;

Ta₂ O₅ ;

TiO₂ ;

SrTiO₃ ;

ZnO;

PZT, and combinations thereof.