Manufacture of trench-gate semiconductor devices

• US 6,087,224 A
• Filed: 04/15/1999
• Issued: 07/11/2000
• Est. Priority Date: 04/17/1998
• Status: Active Grant

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Luo, JiKui
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/292,406
• Time in Patent Office: 453 Days
• Field of Search: 438/268, 438/270, 438/271, 438/272, 438/212, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66348 with a recessed gate

Abstract

The manufacture of a trench-gate semiconductor device, for example a MOSFET or IGBT, includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), and later forming a second mask (52) having a smaller window (52a) by providing sidewall extensions (52b) on the first mask (51). A source region (13) is formed by dopant (63) introduced via the first window (51a), whereas a trench (20) is etched at the smaller window (52a) to extend through a body region (15) and into an underlying portion of a drain region (14). The gate (11) is provided in the trench (20) adjacent to where the channel (12) of the device is accommodated. After removing the second mask (52), a source electrode (23) is provided to contact the source region (13) and an adjacent region (15) of the body (10) at the surface (10a). This method permits the use of self-aligned masking techniques while providing good reproduceability in the doping of the source region (13) and adjacent region (15) and in the contact area of the source electrode (23) with both the source region (13) and the adjacent region (15).

Claims

1. A method of manufacturing a trench-gate semiconductor device having source and drain regions of a first conductivity type which are separated by a channel-accommodating region adjacent to the trench-gate, including the steps of:

(a) forming at a surface of a semiconductor body a first mask having a first window at an area of the body,

(b) forming the source region by introducing dopant of the first conductivity type into the said area via the first window,

(c) forming on the body a second mask having a second window smaller than the first window by providing sidewall extensions on the first mask at the first window,

(d) etching a trench into the body at the second window to extend through a body region and into an underlying portion of the drain region,

(e) depositing material in the trench to provide the gate adjacent to where the channel is accommodated in the body, and

(f) providing a source electrode on the body after removing the second mask so as to expose the source region and an adjacent surface region of the body for contacting by the source electrode.

2. A method as claimed in claim 1, wherein the step (b) is carried out before the step (c), and the trench is etched in step (d) through the source region and through a remaining underlying thickness of the body region and so into the underlying portion of the drain region.

3. A method as claimed in claim 1, wherein the first mask and the sidewall extensions are of differently-etchable materials, the sidewall extensions are etched away after the step (e) to leave at least a part of the first mask at the surface of the body, after which the step (b) is carried out to form the source region.

4. A method as claimed in claim 1, wherein the channel-accommodating region is a region is of an opposite, second conductivity type.

5. A method as claimed in claim 4, wherein dopant of the second conductivity type is introduced into the body before step (c) to provide the channel-accommodating region of the second conductivity type.

6. A method as claimed in claim 1, wherein dopant of the second conductivity type is introduced locally into the body before the step (a) at an area of the body at which the first mask is provided in the step (a), the local dopant introduction serving to provide the device with a localised region of the second conductivity type which is of higher conductivity than the channel-accommodating region adjacent to the trench, is separated by the channel-accommodating body region from the trench formed in step (d), and provides the said adjacent surface region which is contacted by the source electrode in step (f).

7. A method as claimed in claim 6, wherein the dopant forming the localised region is diffused to a greater depth in the body than the channel-accommodating region, before forming the source region in step (b).

8. A method as claimed in claim 1, wherein silicon material is deposited on an insulating layer in the trench to form the gate in step (e).

9. A method as claimed in claim 8, wherein the first mask comprises silicon nitride, silicon nitride is deposited and etched back to form the sidewall extensions of the first mask in step (c), and an upper part of the deposited silicon material in the trench is oxidised to provide an insulating overlayer over the gate while using the silicon nitride of the sidewall extensions and of the first mask to mask underlying areas of the body against oxidation.

10. A method as claimed in claim 1, wherein an insulating overlayer is formed over the gate before step (f), and the source electrode provided in step (f) extends on the surface of the body and also on the insulating overlayer.