Fabrication method of lateral double diffused MOS transistors

• US 6,087,232 A
• Filed: 08/18/1998
• Issued: 07/11/2000
• Est. Priority Date: 10/28/1997
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (SoftBank Group Corp.)
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Koo, Jin Gun, Kim, Sang Ki, Kim, Jong Dae, Nam, Kee Soo
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/135,645
• Time in Patent Office: 693 Days
• Field of Search: 438/297, 438/276, 438/289, 438/286, 438/298, 148/DIG. 126
• US Class Current: 438/289
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.

Claims

1. A method for manufacturing a double RESURF (Reduced SURface Field) LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) devices, said method comprising the steps of:

(a) forming a drift region of a second conductive type in an epitaxial layer of a first conductive type having a silicon substrate of a same conductive type;

(b) sequentially forming a pad oxide and a nitride pattern;

(c) forming a field oxide and a convex region underlying the nitride pattern using an LOCOS (local oxidation) process used the nitride pattern as a mask, and removing the nitride pattern;

(d) forming a tapered top layer of the first conductive type on the surface of said drift region using said field oxide as an ion-implanting mask;

(e) forming a TEOS oxide pattern of multi-layer structure using a chemical vapor deposition (CVD) method for exposing the portion of said epitaxial layer, said drift region and said top layer; and

(f) forming a gate electrode and source/drain regions.

2. A method for making double RESURF LDMOS transistor of claim 1, wherein said TEOS oxide is made of a three-layer structure each having an etching rate which is different from each other.

3. A method for making double RESURF LDMOS transistor of claim 2, wherein said TEOS oxide of three-layer structure consists of a thermally grown oxide, a thick TEOS oxide layer and a thin TEOS oxide layer.

4. (Amended) A method for making double RESURF LDMOS transistor of claim 3, wherein the etching rate of said thin TEOS oxide of upper layer is faster than that of the thick TEOS oxide of lower layer.

5. A method for making double RESURH\F LDMOS transistor of claim 3, wherein a thickness of the thermal oxide ranges from 200 to 500 Å

, a thickness of the TEOS oxide annealed at 850°

C. ranges from 5000 to 8000 Å

, and a thickness of the thin TEOS oxide ranges from 2000 to 300 Å

.