Chip scale package

• US 6,087,586 A
• Filed: 04/07/1998
• Issued: 07/11/2000
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Caesar Technology, Inc.
• Original Assignee: Caesar Technology, Inc.
• Inventors: Chen, Shih-Li
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): WALKENHORST, DAVID W
• Application Number:
  US09/055,750
• Time in Patent Office: 826 Days
• Field of Search: 174/52.2, 174/52.3, 174/52.4, 257/705, 257/712, 257/713, 257/693
• US Class Current: 174/556
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portion coupled to a bonding point on the top surface of the IC chip, and an outer lead portion bent and contoured in such a way that to follow the shape of the outside surface of the package frame. The lead further includes a connecting segment extending between the inner lead portion and the outer lead portion. Under heat induced stress, an angle between the connecting segment and the wall of the package frame changes causing displacement of the IC chip from its original position, and the gap between the surfaces of the IC chip and the package frame absorbs deviations in position of the IC chip, to cushion the stress effect.

Claims

1. A chip scale package for packaging an IC chip, comprising:

an IC chip having a top surface, a bottom surface, and side surfaces extending between said top and bottom surfaces, at least a pair of spaced bonding points being disposed on said top surface of said IC chip;

a package frame having opposite side walls, each extending along a respective one of said side surfaces of said IC chip, said package frame further having bottom beams extending beneath said bottom surface of said IC chip from a lower portion of said side walls of said package frame, said side walls of said package frame having respective upper portions extending above said top surface of said IC chip, a first gap being defined between said side surfaces of said IC chip and said side walls of said package frame, and a second gap being defined between said bottom surface of said IC chip and said bottom beams of said package frame;

at least a pair of substantially identical leads electrically coupled to respective said bonding points, and extending therefrom in opposite directions, each of said leads having;

an inner lead portion attached to said top surface of said IC chip,

an outer lead portion bent to follow a contour of outside surface of a respective one of said side walls and said bottom beams of said package frame, and

a connecting segment coupled between said inner lead portion and said outer lead portion and extending in slanted mutual relationship thereto between substantially said top surface of said IC chip and said upper portion of said side walls of said package frame, an angle being formed between said connecting segment and said side walls of said package frame;

said angle and said first and second gaps defined between said IC chip and said package frame changing in response to induced stress, thereby cushioning said stress.

2. The chip scale package according to claim 1, wherein said connecting segment is connected to a respective one of said pair of bonding points through said inner lead.

3. The chip scale package according to claim 2, wherein said connecting segment is further connected to said respective one of said pair of bonding points through a bonding wire.

4. The chip scale package according to claim 1, wherein said package frame is made of electrically conductive material provided with electrical insulation on a surface thereof to thereby lower induction of said outer lead portion.

5. The chip scale package according to claim 1, wherein said package frame is made of a material having high heat dissipation capability to thereby dissipate the heat generated by said IC chip.

6. The chip scale package according to claim 1, further including a hook member extending at a respective end of said outer lead portion and projected towards said bottom surface of said IC chip, said hook member preventing said package frame from displacement beyond an assigned region.

7. The chip scale package according to claim 1, wherein magnitudes of said first and second gaps and said angle are in such a range that a stress caused by a difference in coefficient of thermal expansion between said IC chip and said package frame can be cushioned.