Step-up/step-down switching regulators and pulse width modulation control therefor

• US 6,087,816 A
• Filed: 06/29/1999
• Issued: 07/11/2000
• Est. Priority Date: 06/29/1999
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Volk, Karl Richard
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/342,323
• Time in Patent Office: 378 Days
• Field of Search: 323/220, 323/222, 323/268, 323/271, 323/282, 323/283
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

Step-up/step-down switching regulators and pulse width modulation control therefor which can provide a high output current, high efficiency, use physically smaller inductor and transistors, have lower output voltage ripple, excellent line and load regulation stability and very fast transient response. The modulation control includes three operating states. The improved operating characteristics are obtained by including, as one of the operating states, the direct flow of current from the input of the regulator to the output of the regulator. This allows delivery of current from the inductor to the output a greater percentage of the time than in the prior art. An exemplary embodiment and exemplary method of operation are described.

Claims

1. A converter for step-up and step-down operation having a converter input, a converter output and a common connection, comprising:

an inductor having first and second connections;

a first transistor coupled between the converter input and the first inductor connection;

a first rectifying device coupled between the first inductor connection and the common connection;

a second transistor coupled between the second inductor connection and the common connection;

a second rectifying device coupled between the second inductor connection and the converter output;

a controller controlling the state of conduction of the first and second transistors responsive to a compensated converter output and a clock signal, the controller having three states of operation, a first state turning the first and second transistors off, a second state turning the first and second transistors on, and a third state turning the first transistor on and second transistor off, the controller switching from the third state to the first state on clock pulses occurring when the compensated converter output indicates an over regulation condition and switching back to the third state when the compensated converter output changes to indicate an under regulation condition, and the controller switching from the third state to the second state on clock pulses occurring when the compensated converter output indicates an under regulation condition and switching back to the third state when the compensated converter output changes to indicate an over regulation condition.

2. The converter of claim 1 wherein the controller is comprised of logic gates and inverters.

3. The converter of claim 1 wherein the controller, when switched into the first or the second state, maintains the respective state for at least a minimum period of time, irrespective of any change in the compensated converter output during that minimum period of time.

4. The converter of claim 3 wherein the minimum period of time is substantially equal to the period of the clock pulse.

5. The converter of claim 4 wherein the clock signal has a duty cycle of approximately 10 percent.

6. A method of operating a converter having a converter input, a converter output and a common connection, the converter also having an inductor having first and second connections, a first transistor coupled between the converter input and the first inductor connection, a first rectifying device coupled between the first inductor connection and the common connection, a second transistor coupled between the second inductor connection and the common connection and a second rectifying device coupled between the second inductor connection and the converter output, comprising:

controlling the state of conduction of the first and second transistors responsive to a compensated converter output and a clock signal by;

a) switching the first and second transistors off on clock pulses occurring when the compensated converter output indicates an over regulation condition and then switching the first transistor on when the compensated converter output changes to indicate an under regulation condition; and

,

b) switching the first and second transistors on clock pulses occurring when the compensated converter output indicates an under regulation condition and switching the second transistor off when the compensated converter output changes to indicate an over regulation condition.

7. The method of claim 6 wherein in subparagraph a), the first and second transistors are both switched off for at least a minimum period of time, and in subparagraph b), the first and second transistors are both switched on for at least a minimum period of time, all irrespective of any change in the compensated converter output during that minimum period of time.

8. The converter of claim 7 wherein the minimum period of time is substantially equal to the period of the clock pulses.

9. The converter of claim 8 wherein the clock signal has a duty cycle of approximately 10 percent.