Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry

• US 6,087,842 A
• Filed: 04/29/1996
• Issued: 07/11/2000
• Est. Priority Date: 04/29/1996
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies Europe BV (Agilent Technologies, Inc.)
• Inventors: Parker, Kenneth P., McDermid, John E.
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US08/639,580
• Time in Patent Office: 1,534 Days
• Field of Search: 324/684, 324/158.1, 324/754, 324/763, 324/765, 324/538
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/312 by capacitive methods
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An electromagnetic probe is integrated within an integrated circuit or mounted within an IC package to provide a capability for testing continuity between the integrated circuit and a substrate to which the integrated circuit is mounted. In a first embodiment, capacitive test probes are integrated within the integrated circuit, underneath bonding pads. In a second embodiment, Hall-effect devices are integrated within the integrated circuit underneath bonding pads. In a third embodiment, an inductive loop is integrated within the integrated circuit underneath bonding pads. In a fourth embodiment, an IC package assembly includes an internal capacitive test probe for electrical continuity testing. An internal shield may also be used as a capacitive test probe. In a fifth embodiment, an IC package assembly includes an inductive loop within the package for electrical continuity testing. The integrated or intrapackage test probes provide electromagnetic coupling to bonding pads or to a lead frame and to bonding wires (if present), to detect whether there is electrical continuity between an integrated circuit bonding pad or lead frame and conductors on an external substrate. The integrated or intrapackage test probes enable continuity testing for direct-bonding with no package, or for a package assembly even if the package assembly includes grounded shielding or a grounded heat sink.

Claims

1. An integrated circuit comprising:

a bonding pad; and

a test probe integrated within the integrated circuit, the test probe positioned to enable magnetic but not ohmic coupling between the test probe and the bonding pad, the test probe adapted for electrical coupling to the integrated circuit, thereby enabling a signal, generated externally of the integrated circuit, to be coupled between the bonding pad and the test probe when no power is being applied to operate the integrated circuit for evaluating electrical continuity of the bonding pad.

2. The integrated circuit of claim 1, wherein the test probe comprises a Hall-effect device.

3. The integrated circuit of claim 1, wherein the test probe comprises a conductive loop.

4. The integrated circuit of claim 1, wherein the test probe comprises a capacitive probe positioned to enable capacitive coupling between the test probe and the bonding pad.

5. The integrated circuit of claim 1, wherein the test probe comprises a magnetic probe positioned to enable magnetic coupling between the test probe and the bonding pad.

6. The integrated circuit of claim 1, wherein the test probe is oriented beneath the bonding pad such that loss of active circuit area of the integrated circuit due to placement of the test probe is prevented.

7. A package for an integrated circuit, the package comprising:

a lead conductively attached to the integrated circuit; and

a test probe located interior to the package and external to the integrated circuit, the test probe not making ohmic contact with the lead, the test probe positioned to enable electromagnetic coupling between the test probe and the lead, the test probe configured such that the electromagnetic coupling is minimized between the test probe and circuitry within the integrated circuit other than the lead, the test probe further configured to be electrically coupled externally of the package, thereby enabling a signal, generated externally of the package, to be coupled to the lead through the test probe.

8. The package of claim 7, wherein the test probe comprises a capacitive test probe positioned to enable capacitive coupling between the capacitive test probe and the lead.

9. The package of claim 8, wherein the integrated circuit is mounted onto a base, and wherein the capacitive test probe is disposed between the lead and the base.

10. The package of claim 8, wherein the capacitive test probe is configured such that the capacitive test probe does not extend over the integrated circuit, thereby minimizing capacitive coupling between the test probe and the integrated circuit.

11. The package of claim 7, wherein the test probe is adapted for sensing a magnetic field and the test probe is positioned to enable magnetic coupling between the test probe and the lead.

12. The package of claim 11, wherein the test probe comprises a conductive loop.

13. The package of claim 7, further comprising a ground shield located interior to the package and external to the integrated circuit, the ground shield being configured to reduce radio frequency interference of the integrated circuit, and wherein the test probe is disposed between the lead and the ground shield.

14. The package of claim 7, further comprising a heat sink located interior to the package and external to the integrated circuit, the heat sink being configured to assist in temperature control of the integrated circuit, and wherein the test probe is disposed between the lead and the heat sink.

15. The package of claim 14, wherein the means for externally electrically coupling is a hole formed through the heat sink.

16. The package of claim 7, wherein the test probe is configured as a conductive shield which is adaptable between a grounding configuration and a testing configuration, in the grounding configuration the test probe being grounded such that the test probe reduces radio frequency interference of the integrated circuit, and in the testing configuration the test probe being configured as a capacative probe for receiving the externally generated signal.

17. The package of claim 16, further comprising means for externally electrically coupling the signal to the test probe.

18. A method for evaluating electrical continuity of a bonding pad of an integrated circuit comprising the steps of:

providing an integrated circuit having a bonding pad;

providing a test probe;

positioning the test probe within the integrated circuit such that the test probe is positioned to enable magnetic but not ohmic coupling with the bonding pad, the test probe being adapted for electrical coupling to the integrated circuit;

generating a signal externally of the integrated circuit;

applying the signal to the test probe;

coupling the bonding pad and the test probe when no power is being applied to operate the integrated circuit; and

evaluating a response to the signal.

19. The method of claim 18, wherein the step of positioning the test probe comprises positioning the test probe beneath the bonding pad such that loss of active circuit area of the integrated circuit due to placement of the test probe is prevented.

20. A method for evaluating electrical continuity of a lead of an integrated circuit, the integrated circuit being provided within a package, the method comprising the steps of:

providing a package having an integrated circuit therein, the integrated circuit having a lead conductively attached to the integrated circuit;

providing a test probe;

positioning the test probe interior to the package and external to the integrated circuit such that the test probe does not make ohmic contact with the lead, while being positioned to enable electromagnetic coupling between the test probe and the lead, the test probe being configured such that the electromagnetic coupling is minimized between the test probe and circuitry within the integrated circuit other than the lead;

electrically coupling the test probe externally of the package;

generating a signal externally of the package;

coupling the signal to the lead through the test probe; and

evaluating a response to the signal.

21. The method of claim 20, wherein the step of providing a package comprises providing a ground shield located interior to the package and external to the integrated circuit, the ground shield being configured to reduce radio frequency interference of the integrated circuit, and wherein the step of positioning the test probe comprises disposing the test probe between the lead and the ground shield.

22. The method of claim 20, wherein the step of providing a package comprises providing a heat sink located interior to the package and external to the integrated circuit, the heat sink being configured to assist in temperature control of the integrated circuit, and wherein the step of positioning the test probe comprises disposing the test probe between the lead and the heat sink.

23. The method of claim 20, wherein the step of providing a test probe comprises the step of providing a test probe configured as a conductive shield, the test probe being adaptable between a grounding configuration and a testing configuration, in the grounding configuration the test probe being grounded such that the test probe reduces radio frequency interference of the integrated circuit, and in the testing configuration the test probe being configured as a capacative probe for receiving the externally generated signal.