Impedance control circuit

• US 6,087,847 A
• Filed: 07/29/1997
• Issued: 07/11/2000
• Est. Priority Date: 07/29/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mooney, Stephen R., Kennedy, Joseph T., Haycock, Matthew B.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/902,345
• Time in Patent Office: 1,078 Days
• Field of Search: 326/83, 326/86, 326/30, 333/124, 333/173, 333/32, 327/312, 327/316, 327/323, 327/328, 327/108
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/017545 Coupling arrangements; Impedance matching circuits

Abstract

Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

Claims

1. An integrated circuit comprising:

a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance.

2. The integrated circuit of claim 1, wherein said digital feedback control circuit also includes the capability to adjust the slew rate of said interface circuit output buffer.

3. The integrated circuit of claim 2, wherein said digital feedback control circuit includes the capability to adjust the impedance of said interface circuit output buffer on-the-fly.

4. The integrated circuit of claim 3, wherein the capability to adjust the impedance of said interface circuit output buffer on-the-fly comprises the capability to adjust the impedance of the non-transmitting side of said interface circuit output buffer on-the-fly.

5. The integrated circuit of claim 3, wherein said digital feedback control circuit to adjust the impedance of said interface circuit output buffer comprises a digital feedback control circuit to approximately match the impedance of said non-data signal output buffer with the impedance of the external coupling.

6. The integrated circuit of claim 1, wherein said external coupling comprises at least one resistor.

7. The integrated circuit of claim 1, wherein said digital feedback control circuit comprises a source termination digital feedback control circuit.

8. The integrated circuit of claim 1, wherein said interface circuit output buffer comprises an output buffer in which at least some of the transistors are series gated.

9. The integrated circuit of claim 1, wherein said interface circuit output buffer includes an amplifier configuration with a plurality of legs, said legs being sized so that their weighting to adjust the effective impedance of the output buffer is substantially binary.

10. A method of adjusting the impedance of an interface circuit output buffer comprising:

digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance;

and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

11. The method of claim 10, wherein digitally adjusting the impedance of the interface circuit output buffer includes also digitally adjusting the slew rate of the interface circuit output buffer.

12. The method of claim 10, wherein digitally adjusting the impedance of the interface circuit output buffer includes digitally adjusting the impedance on-the-fly.

13. The method of claim 12, wherein digitally adjusting the impedance of the interface circuit output buffer on-the-fly comprises digitally adjusting the impedance of the non-transmitting side of the interface circuit output buffer on-the-fly.

14. The method of claim 10, wherein adjusting the impedance of the non-data signal output buffer comprises approximately matching the impedance of the non-data signal output buffer with the impedance of the external coupling.

15. The method of claim 14, wherein the externally coupling comprises at least one resistor.

16. The method of claim 10, wherein digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance comprises digitally adjusting the impedance of the non-data signal output buffer so that the external impedance is source terminated.

17. The method of claim 10, wherein digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance comprises digitally adjusting the impedance in binary weighted increments.