Method and apparatus for configuring a semiconductor device for compatibility with multiple logic interfaces

• US 6,087,851 A
• Filed: 04/30/1998
• Issued: 07/11/2000
• Est. Priority Date: 04/30/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chi-wook, Kang, Kyung-woo
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/070,894
• Time in Patent Office: 803 Days
• Field of Search: 326/31, 326/33, 326/37, 326/62, 326/63, 326/80, 326/82, 326/86, 395/500
• US Class Current: 326/63
• CPC Class Codes: H03K 19/017581 programmable

Abstract

A semiconductor device can be configured for compatibility with different system level interfaces, e.g., LVTTL or SSTL, after assembly, thereby eliminating the need for bonding options and reducing the cost of manufacturing the device. The device includes an interface dependent circuit that operates with a selected interface in response to one or more interface enable signals. Several alternative embodiments include interface control circuits and mode register circuits for generating the interface enable signals responsive to a row address and control signals such as RAS, CAS, WE, and CS. Some embodiments also include a switching network that allows an input buffer to use an internally generated reference voltage for one interface and an externally applied reference voltage for a second interface.

Claims

1. A semiconductor device comprising:

an interface control circuit for activating one of a plurality of interface enable signals responsive to at least one input signal for selecting an interface mode, and an address signal; and

an interface dependent circuit coupled to the interface control circuit for receiving the plurality of interface enable signals and operating in a selected interface mode responsive to the plurality of interface enable signals, whereby the semiconductor device is compatible with a plurality of system level interfaces.

2. A semiconductor device comprising:

an interface control circuit for activating one of a plurality of interface enable signals responsive to at least one input signal for selecting an interface mode; and

an interface dependent circuit coupled to the interface control circuit for receiving the plurality of interface enable signals and operating in a selected interface mode responsive to the plurality of interface enable signals, whereby the semiconductor device is compatible with a plurality of system level interfaces;

wherein the interface control circuit comprises;

a register circuit for receiving a row address signal and generating an interface mode row address signal responsive to the row address signal and an interface selection mode signal;

an interface selection mode signal generator coupled to the register circuit for generating the interface selection mode signal responsive to the at least one input signal for selecting an interface mode; and

an interface enable signal generator coupled to the register circuit for decoding the interface mode row address signal and activating one of the plurality of interface enable signals.

3. The semiconductor device of claim 2 wherein the interface selection mode signal generator activates the interface selection mode signal when a row address strobe signal, a column address strobe signal, a write enable signal and a chip selection signal are all active.

4. The semiconductor device of claim 2 wherein the register circuit comprises:

a first inverter for inverting the row address signal;

a transmission gate coupled to the first inverter for transmitting the output from the first inverter responsive to the interface selection mode signal;

a latch coupled to the transmission gate for latching the signal from the transmission gate;

a precharge circuit coupled to the latch for precharging an input port of the latch; and

a drive circuit coupled to the latch for driving the output from the latch, thereby generating the interface mode row address signal.

5. The semiconductor device of claim 4 wherein the precharge circuit is coupled between a power port and the input port of the latch, and includes a transistor that is gated by a signal that is activated before the interface selection mode signal is active and deactivated when the interface selection mode signal is active.

6. The semiconductor device of claim 2 wherein the interface enable signal generator comprises:

a first logic gate for receiving three row address signals from the register circuit and generating a first interface enable signal which is active when the three row address signals are all inactive;

a second logic gate for receiving the three row address signals from the register circuit and generating a second interface enable signal which is active when two of the three row address signals are active and the remaining row address signal is inactive;

a third logic gate for receiving the three row address signals from the register circuit and generating a third interface enable signal which is active when the three row address signals are all active; and

a fourth logic gate for coupled to the first, second, and third logic gates for generating a fourth output signal responsive to the first second and third interface enable signals.

7. A semiconductor device comprising:

a mode register setting circuit for activating one of a plurality of interface enable signals responsive to an input address and a plurality of control signals; and

an interface dependent circuit coupled to the mode register setting circuit for receiving the plurality of interface enable signals and operating in a selected interface mode responsive to the plurality of interface enable signals, whereby the semiconductor device is compatible with a plurality of system level interfaces.

8. A semiconductor device comprising:

a mode register setting circuit for activating one of a plurality of interface enable signals responsive to an input address and a plurality of control signals; and

an interface dependent circuit coupled to the mode register setting circuit for receiving the plurality of interface enable signals and operating in a selected interface mode responsive to the plurality of interface enable signals, whereby the semiconductor device is compatible with a plurality of system level interfaces;

wherein;

the plurality of control signals includes a row address strobe signal, a column address strobe signal, a write enable signal, and chip selection signal; and

the mode register setting circuit activates one of the plurality of interface enable signals when the control signals are all active.

9. A semiconductor device comprising:

a mode register setting circuit for activating one of a plurality of interface enable signals responsive to an input address and a plurality of control signals; and

an interface dependent circuit coupled to the mode register setting circuit for receiving the plurality of interface enable signals and operating in a selected interface mode responsive to the plurality of interface enable signals, whereby the semiconductor device is compatible with a plurality of system level interfaces;

wherein the mode register setting circuit comprises;

a mode register for receiving and storing a row address signal and generating a mode row address signal responsive to an interface selection mode signal; and

an interface enable signal generator coupled to the mode register for receiving and decoding the mode row address signal and activating one of the plurality of interface enable signals responsive to the mode row address signal.

10. The semiconductor device of claim 9 wherein the mode register comprises:

a first inverter for inverting the row address signal;

a transmission gate coupled to the first inverter for transmitting the output from the first inverter responsive to the interface selection mode signal;

a latch coupled to the transmission gate for latching the signal from the transmission gate;

a precharge circuit coupled to the latch for precharging an input port of the latch; and

a drive circuit coupled to the latch for driving the output from the latch, thereby generating the mode row address signal.

11. The semiconductor device of claim 10 wherein the precharge circuit is coupled between a power port and the input port of the latch, and includes a transistor that is gated by a signal that is activated before the interface selection mode signal is active and deactivated when the interface selection mode signal is active.

12. A semiconductor device compatible with a first interface, the device comprising:

an input buffer;

a reference voltage generator;

a pad for receiving a reference voltage;

a control circuit for generating an interface enable signal;

an interface dependent circuit coupled to the control circuit for operating with a second interface responsive to the interface enable signal;

a first switch coupled between the reference voltage generator and the input buffer for transmitting the reference voltage from the reference voltage generator to the input buffer responsive to the interface enable signal; and

a second switch coupled between the pad and the input buffer for transmitting the reference voltage from the pad to the input buffer responsive to the interface enable signal;

whereby the semiconductor device can be configured to be compatible with the first and second interfaces responsive to interface selection information.

13. The semiconductor device of claim 12 wherein the control circuit includes:

an interface control circuit for activating an interface control signal when an interface selection mode is set; and

an enable circuit coupled to the interface control circuit for generating an interface enable signal responsive to the interface control signal.

14. The semiconductor device of claim 13 wherein the interface control circuit comprises:

an interface selection signal generator for generating an interface selection signal that is active when a predetermined number of control signals for controlling the operation of the semiconductor device are active;

an interface mode signal generator for generating an interface mode signal responsive to a combination of row address signals; and

an interface control signal generator coupled to the interface selection signal generator and the interface mode signal generator for generating the interface control signal responsive to the interface selection signal and the interface mode signal.

15. The semiconductor device of claim 14 wherein the interface selection signal generator activates the interface selection signal when a row address strobe signal, a column address strobe signal, a write enable signal, and a chip selection signal are all active.

16. The semiconductor device of claim 13 wherein the enable circuit comprises:

an inverter for inverting a row address signal;

a transmission gate coupled to the invertor for transmitting the output from the inverter responsive to the interface control signal;

a latch coupled to the transmission gate for latching the signal from the transmission gate;

a precharge circuit coupled to the latch for precharging an input port of the latch; and

a drive circuit coupled to the latch for driving the output from the latch, thereby generating the interface enable signal.

17. The semiconductor device of claim 16 wherein the precharge circuit is coupled between a power port and the input port of the latch, and includes a transistor that is gated by a signal that is activated before the interface selection mode signal is active and deactivated when the interface selection mode signal is active.

18. The semiconductor device of claim 12 wherein the first switch is a transmission gate which is deactivated when the interface enable signal is active such that the transmission gate does not transmit the reference voltage from the reference voltage generator to the input buffer.

19. The semiconductor device of claim 12 wherein the second switch is a transmission gate which is enabled when the interface enable signal is active so as to transmit the reference voltage from the pad to the input buffer.

20. A semiconductor device compatible with a first interface, the device comprising:

an input buffer;

a reference voltage generator;

a pad for receiving a reference voltage;

a mode register setting circuit for activating an interface enable signal responsive to an input address and a plurality of control signals;

an interface dependent circuit coupled to the mode register setting circuit for operating with a second interface responsive to the interface enable signal;

a first switch coupled between the reference voltage generator and the input buffer for transmitting the reference voltage from the reference voltage generator to the input buffer responsive to the interface enable signal; and

a second switch coupled between the pad and the input buffer for transmitting the reference voltage from the pad to the input buffer responsive to the interface enable signal;

whereby the semiconductor device can be configured to be compatible with the first and second interfaces responsive to interface selection information.

21. The semiconductor device of claim 20 wherein the mode register setting circuit comprises:

a mode register for receiving and storing row address signal and generating a mode row address signal responsive to an interface selection mode signal; and

an enable signal generator coupled to the mode register for receiving and decoding the mode row address signal and activating a corresponding interface enable signal responsive to the mode row address signal.

22. The semiconductor device of claim 21 wherein the mode register comprises:

a first inverter for inverting the row address signal;

a transmission gate coupled to the first inverter for transmitting the output from the first inverter responsive to the interface selection mode signal;

a latch coupled to the transmission gate for latching the signal from the transmission gate;

a precharge circuit coupled to the latch for precharging an input port of the latch; and

a drive circuit coupled to the latch for driving the output from the latch, thereby generating the mode row address signal.

23. The semiconductor device of claim 22 wherein the precharge circuit is coupled between a power port and the input port of the latch, and includes a transistor that is gated by a signal that is activated before the interface selection mode signal is active and deactivated when the interface selection mode signal is active.

24. The semiconductor device of claim 20 wherein the first switch is a transmission gate which is deactivated when the interface enable signal is active such that the transmission gate does not transmit the reference voltage from the reference voltage generator to the input buffer.

25. The semiconductor device of claim 20 wherein the second switch is a transmission gate which is enabled when the interface enable signal is active so as to transmit the reference voltage from the pad to the input buffer.

26. A method for driving a semiconductor device that is compatible with a plurality of interfaces, the method comprising:

(a) setting the device in an interface selection mode;

(b) activating one of a plurality of interface enable signals responsive to an interface selection mode signal and an address signal; and

(c) setting the operation of an interface dependent circuit responsive to the active interface enable signal such that the interface dependent circuit operates with a selected interface.

27. A method for driving a semiconductor device that is compatible with a plurality of interfaces, the method comprising:

(a) activating a mode register setting circuit responsive to a plurality of control signals;

(b) inputting a row address to the mode register setting circuit when the mode register setting circuit is activated;

(c) setting an interface selection mode according to the row address;

(d) activating one of a plurality of interface enable signals responsive to the row address; and

(e) setting the operation of an interface dependent circuit responsive to the active interface enable signal such that the interface dependent circuit operates with a selected interface.

28. A method for driving a semiconductor device that is compatible with a plurality of interfaces, the method comprising:

(a) setting the device in an interface selection mode;

(b) generating an interface enable signal;

(c) setting the operation of an interface dependent circuit responsive to the interface enable signal such that the interface dependent circuit operates with a selected interface;

(d) isolating a reference voltage generated inside the device from an input buffer; and

(e) applying a reference voltage from outside of the device to the input buffer.

29. A method for driving a semiconductor device that is compatible with a plurality of interfaces, the method comprising:

(a) enabling a mode register setting circuit responsive to a plurality of control signals;

(b) inputting a row address when the mode register setting circuit is activated;

(c) setting an interface selection mode responsive to the row address;

(d) generating an interface enable signal responsive to the row address;

(e) setting the operation of an interface dependent circuit responsive to the interface enable signal such that the interface dependent circuit operates with a selected interface;

(f) isolating a reference voltage generated inside the device from an input buffer; and

(g) applying a reference voltage from outside of the device to the input buffer.