Scalable graphics processor architecture
First Claim
1. A scalable graphics processor architecture comprising:
- a base graphics architecture;
wherein the base graphics architecture further comprises;
a plurality of rendering processors;
a first bus coupled to the plurality of processors for providing I/O signals to the processors;
a first expansion connector coupled to the first bus;
a plurality of video digital to analog converters (VDACs), each of the VDACs adapted for driving a display;
a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween;
a switch coupled to the plurality of processors, the switch being for selectively driving the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and such that the rendering processors drive all of the plurality of VDACs when the switch is in a second mode; and
a second expansion connector coupled to the switch for providing image data to at least one of the plurality of digital analog converters; and
an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture.
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Abstract
A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. In a second aspect, the architecture comprises a plurality of rendering processors, a first bus coupled to the plurality of processors for providing I/O signals to the processors; and a plurality of digital to analog converters (VDACs). In this aspect, each of the VDACs are adapted for driving a display. The architecture further includes a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to a plurality of processors. The switch selectively drives the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and the rendering processors drive all of the plurality of VDACs when the switch is in a second mode. Through the use of this architecture, the graphics processor system is expandable to allow more rendering processors to be added as well as allowing the processors to drive multiple VDACs or drive a single VDAC together.
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Citations
20 Claims
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1. A scalable graphics processor architecture comprising:
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a base graphics architecture;
wherein the base graphics architecture further comprises;
a plurality of rendering processors;
a first bus coupled to the plurality of processors for providing I/O signals to the processors;
a first expansion connector coupled to the first bus;
a plurality of video digital to analog converters (VDACs), each of the VDACs adapted for driving a display;
a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween;a switch coupled to the plurality of processors, the switch being for selectively driving the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and such that the rendering processors drive all of the plurality of VDACs when the switch is in a second mode; and
a second expansion connector coupled to the switch for providing image data to at least one of the plurality of digital analog converters; andan expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A scalable graphics processor architecture comprising:
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a plurality of rendering processors; a first bus coupled to the plurality of processors for providing I/O signals to the processors; a plurality of video digital to analog converters (VDACs), each of the VDACs adapted for driving a display; a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to plurality of processors, the switch being for selectively driving the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and such that the rendering processors drive all of the plurality of VDACs when the switch is in a second mode. - View Dependent Claims (10, 11, 12, 13)
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14. A scalable graphics processor architecture comprising:
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a plurality of rendering processors; a first bus coupled to the plurality of processors for providing I/O signals to the processors; a first expansion connector coupled to the first bus; a plurality of video digital to analog converters (VDACs), each of the VDACs adapted for driving a display; a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; a switch, coupled to plurality of processors, the switch being for selectively driving the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and such that the rendering processors drive all of the plurality of VDACs when the switch is in a second mode; and a second expansion connector coupled to the switch for providing image data to at least one of the plurality of digital analog converters. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification