High definition multimedia display

• US 6,088,045 A
• Filed: 07/22/1991
• Issued: 07/11/2000
• Est. Priority Date: 07/22/1991
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Choi, Sung Min, Peevers, Alan Wesley, Pittas, John Louis, Lumelsky, Leon
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): NGUYEN, CHANH DUY
• Application Number:
  US07/733,950
• Time in Patent Office: 3,277 Days
• Field of Search: 340/721, 340/724, 340/814, 358/182, 358/183, 345/115, 345/121, 345/127, 345/200, 345/201, 345/189, 345/190, 345/192, 345/193, 345/185-213, 348/5
• US Class Current: 345/531
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.

Claims

1. Image display apparatus, comprising:

image display control means for programmably generating image display control signals;

image buffer means having a plurality of addressable locations for storing image pixel data, said image buffer means having an output for coupling the stored image pixel data to an input of an image display means having a display screen, said image buffer means being configurable for both image pixel data write and image pixel data read accesses into one of a plurality of different x storage location by y storage location by z-bit configurations;

means, having an input coupled to said output of said image buffer means, for converting image pixel data read from said image buffer means to electrical signals for driving the input of the image display means, said converting means including means, responsive to control signals generated by said image display control means, for generating one of a plurality of different timing formats for the electrical signals, wherein a generated one of the plurality of different timing formats is selected as a function of a display resolution of the image display means; and

means, responsive to control signals generated by said image display control means, for configuring said image buffer means for both image pixel data write and image pixel data read accesses into one of said plurality of different x storage location by y storage location by z-bit configurations.

2. Image display apparatus as set forth in claim 1 wherein said configuring means is responsive to control signals generated by said image display control means for configuring said image buffer means as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer;

or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer;

or as four, 2048 location by 1024 location by 24-bit buffers and two 2048 location by 1024 location by 16-bit buffers.

3. Image display apparatus as set forth in claim 2 wherein the 24-bit buffers each store R,G,B pixel data, and wherein the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value.

4. Image display apparatus as set forth in claim 3 wherein said converting means includes means for decoding a CI value and an associated WID value, output from said image buffer means, for providing R,G,B pixel data at an output of the decoding means.

5. Image display apparatus as set forth in claim 1 and further comprising:

first interface means having an input for receiving image pixel data expressed in a first format and having an output coupled to said image buffer means for storing the received image pixel data in said image buffer means in a R,G,B format;

second interface means having an input for receiving image pixel data expressed in a second format and having an output coupled to said image buffer means for storing the received image pixel data in said image buffer means in the R,G,B format; and

third interface means having an input for receiving image pixel data expressed in the CI and WID a Color Index (CI) and Window Identifier (WID) format and having an output coupled to said image buffer means for storing the received image pixel data in said image buffer means in the CI and WID format.

6. Image display apparatus as set forth in claim 5 wherein said converting means includes means for decoding a CI value and an associated WID value that is output from said image buffer means for providing R,G,B pixel data at an output of the decoding means, and wherein the decoding means further decodes the CI value and the associated WID value to provide a key signal specifying, for an associated image pixel, a contribution of the R,G,B data from the first interface means, a contribution of the R,G,B data from the second interface means, and a contribution of the R,G,B, data output by the decoding means.

7. Image display apparatus as set forth in claim 5 wherein said first interface means includes means for coupling to a communications bus for receiving the image pixel data therefrom, and wherein the communications bus transfers image pixel data to the first interface means in a raster scan order.

8. Image display apparatus as set forth in claim 7 wherein the communications bus further transfers information to the first interface means for specifying coordinates of an initial display screen location of the image pixel data, and wherein said first interface means includes means for causing said image buffer means to store the image pixel data beginning at an addressable location that corresponds to the coordinate specifying information.

9. Image display apparatus as set forth in claim 5 wherein said second interface means includes means for coupling to a source of a High Definition Television (HDTV) signal, said coupling means including means for converting the HDTV signal to the R,G,B format.

10. Image display apparatus, comprising:

image buffer means having a plurality of addressable locations for storing image pixel data, said image buffer means being configurable for both image pixel data write and image pixel data read accesses into one of a plurality of different x storage location by y storage location by z-bit configurations;

means, having an input coupled to an output of said image buffer means, for converting image pixel data read therefrom to electrical signals suitable for driving an image display means so as to display the image pixels;

first interface means having an input for receiving an image signal expressed in a first format and having an output coupled to said image buffer means for storing the received image signal therein;

second interface means having an input for receiving an image signal expressed in a second format and having an output coupled to said image buffer means for storing the received image signal therein; and

third interface means having an input for receiving an image signal expressed in a third format and having an output coupled to said image buffer means for storing the received image signal therein;

wherein

the image signal stored from said third interface means includes information for specifying, for each displayed image pixel, a contribution from the image signal received by each of the first interface means, the second interface means, and the third interface means.

11. Image display apparatus as set forth in claim 10 wherein said converting means includes means for generating a plurality of different timing formats for the electrical signals for driving image display means having different display resolutions.

12. Image display apparatus as set forth in claim 10 wherein said first interface means includes means for coupling to a communications bus for receiving the image signal expressed in the first format therefrom.

13. Image display apparatus as set forth in claim 12 wherein the communications bus transfers image pixel data to the first interface means in a raster scan order.

14. Image display apparatus as set forth in claim 13 wherein the communications bus further transfers information to the first interface means for specifying coordinates of an initial display screen location of the image pixel data, and wherein said first interface means includes means for causing said image buffer means to store the image pixel data beginning at an addressable location that corresponds to the coordinate specifying information.

15. Image display apparatus as set forth in claim 12 wherein the communications bus operates in accordance with an electrical specification known as a High Performance Parallel Interface (HPPI).

16. Image display apparatus as set forth in claim 10 wherein said second interface means includes means for coupling to a source of a High Definition Television (HDTV) signal, said coupling means including means for converting the HDTV signal to a R,G,B digital signal prior to the storage of the received image signal within said image buffer means.

17. Image display apparatus as set forth in claim 16 wherein said coupling means further includes means for coupling the converted HDTV signal to means for transmitting the converted HDTV signal to a communications bus.

18. Image display apparatus as set forth in claim 17 wherein said first interface means includes means for coupling to a communications bus for receiving the image signal expressed in the first format therefrom, and wherein the transmitted converted HDTV signal is received by means external to the image display apparatus and is subsequently transmitted from the external means to the first interface means for reception thereby.

19. Image display apparatus as set forth in claim 10 wherein the first format is a R,G,B format, wherein said second interface means includes means for coupling to a source of a High Definition Television (HDTV) signal, and wherein said second interface means includes means for converting the HDTV signal to the first format prior to the storage of the received image signal within said image buffer means.

20. Image display apparatus as set forth in claim 10 wherein the first format is a R,G,B format, wherein the third format includes information for specifying a color index, and wherein said converting means includes means for converting the color index to the first format.

21. Image display apparatus as set forth in claim 10 wherein the first format is a R,G,B format, wherein second interface means includes means for converting the received image signal to the R,G,B format prior to the storage of the received image signal within said image buffer means, wherein the third format includes information for specifying a color index (CI) and an image display means display screen window identifier (WID), wherein said image buffer means is partitioned into a first buffer means for storing pixel data that specifies two colors of the R,G,B format, and wherein said image buffer means is partitioned into a second buffer means for storing a third color of the R,G,B format and also for storing the information specifying the CI and the WID.

22. Image display apparatus as set forth in claim 21 wherein said converting means includes means for decoding a CI value and an associated WID value, read from the second buffer means, for providing R,G,B pixel data at an output of the decoding means.

23. Image display apparatus as set forth in claim 22 wherein the decoding means further decodes the CI value and the associated WID value to provide a key signal specifying, for an associated image pixel, a contribution of the R,G,B data from the first interface means, a contribution of the R,G,B data from the second interface means, and a contribution of the R,G,B, data output by the decoding means.

24. Image display apparatus as set forth in claim 10 wherein the first format is a R,G,B format, wherein second interface means includes means for converting the received image signal to the R,G,B format prior to the storage of the received image signal within said image buffer means, wherein the third format includes information for specifying a color index (CI) and an image display means display screen window identifier (WID), and further including means, having outputs coupled to said image buffer means, for configuring said image buffer means as

two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer;

or as

two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer;

or as

four, 2048 location by 1024 location by 24-bit buffers and two 2048 location by 1024 location by 16-bit buffers;

wherein

the 24-bit buffers store R,G,B pixel data and the 16-bit buffers store the CI and the WID data.

25. Image display apparatus, comprising:

image display control means for programmably generating image display control signals;

image buffer means having a plurality of addressable locations for storing image pixel data;

means, having an input coupled to an output of said image buffer means, for converting image pixel data output therefrom to electrical signals for driving an image display means so as to display image pixels, said converting means including means, responsive to control signals generated by said image display control means, for generating one of a plurality of different timing formats for the electrical signals for driving an image display means having a specified display resolution; and

means, responsive to control signals generated by said image display control means, for configuring said image buffer means for both image pixel data write and image pixel data read accesses as a function of the specified display resolution;

wherein

said image buffer means is configured as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer;

or as

two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer;

or as

four, 2048 location by 1024 location by 24-bit buffers and two 2048 location by 1024 location by 16-bit buffers.

26. Image display apparatus as set forth in claim 25 wherein the 24-bit buffers each store R,G,B pixel data and wherein the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value.

27. Image display apparatus as set forth in claim 26 wherein said converting means includes means for decoding a CI value and an associated WID value, read from said image buffer means, for providing R,G,B pixel data at an output of the decoding means.

28. Image display apparatus as set forth in claim 27 wherein the decoding means further decodes the CI value and the associated WID value to provide a key signal specifying, for an associated image pixel, a contribution of the R,G,B data from each of the 24-bit buffers and a contribution of the R,G,B, data output by the decoding means.

29. Image display apparatus as set forth in claim 25 and further including means for receiving, from a communications channel, image pixel data therefrom, and further including means, having an input coupled to an output of the receiving means, and an output coupled to the image buffer means, for providing the image pixel data for storage within at least one of the 24-bit buffers.

30. Image display apparatus as set forth in claim 29, wherein said communications channel further transfers information for specifying coordinates of an initial display screen location of the image pixel data, and wherein said apparatus further includes interface means, responsive to said coordinate specifying information, for causing said image buffer means to store the image pixel data beginning at an addressable location that corresponds to the coordinate specifying information.

31. Image display apparatus as set forth in claim 25 and further including means for coupling to a source of a High Definition Television (HDTV) signal, said coupling means including means for converting the HDTV signal to image pixel data, and further including means, having an input coupled to an output of the coupling means, and an output coupled to the image buffer means, for providing the image pixel data for storage within at least one of the 24-bit buffers.

32. Image display apparatus as set forth in claim 31, and further including means for interfacing to the image display control means for receiving from said image display control means information for specifying coordinates of an initial display screen location of the image pixel data, and including interface means, responsive to said coordinate specifying information, for causing said image buffer means to store the image pixel data beginning at an addressable location that corresponds to the coordinate specifying information.

33. Image display apparatus, comprising:

image display control means for programmably generating image display control signals;

image buffer means having a plurality of addressable locations for storing image pixel data, said image buffer means having an output for coupling the stored image pixel data to an input of an image display means having a display screen, said image buffer means being configurable for both image pixel data write and image data pixel read accesses into one of a plurality of different x storage location by y storage location by z-bit configurations;

means, having an input coupled to said output of said image buffer means, for converting image pixel data read from said image buffer means to electrical signals for driving the input of the image display means; and

means, responsive to control signals generated by said image display control means, for configuring said image buffer means for both image pixel data write and image pixel data read accesses into one of said plurality of different x storage location by y storage location by z-bit configurations, wherein one of said configurations corresponds to a stereoscopic image display configuration.