Semiconductor memory device

• US 6,088,281 A
• Filed: 10/20/1998
• Issued: 07/11/2000
• Est. Priority Date: 10/21/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Otsuka, Nobuaki, Miyakawa, Tadashi, Tomita, Naoto
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/175,445
• Time in Patent Office: 630 Days
• Field of Search: 365/225.7, 365/186.09, 365/185.25, 365/203
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A semiconductor memory device for a flash EEPROM includes MOS transistors, each used as a fuse element for storing function control data and having a stacked gate structure in which a floating gate and a control gate are stacked on each other, and a sequence control circuit for pre-charging the drain of a MOS transistor as a fuse element upon reception of a predetermined control signal, reading out data from the MOS transistor after the pre-charge operation, and latching the readout data.

Claims

1. A semiconductor memory device comprising:

a memory cell array;

a memory control section for controlling data read/write with respect to said memory cell array;

a sequence control section for controlling a sequence operation for realizing a function of said memory control section; and

a function control section having at least one fuse circuit storing function control data used by said sequence control section to perform the sequence operation, said function control section executing a fuse sequence of pre-charging said fuse circuit, reading out the function control data after said fuse circuit is precharged, to obtain readout function control data, and latching the readout function control data, in response to at least one of operations including power-on operation and selection of a predetermined function.

2. A device according to claim 1, wherein said function control section comprises a fuse element including a MOS transistor having a stacked gate structure, said fuse element storing the function control data, and a fuse circuit including a fuse element control circuit for pre-charging said fuse element, reading out data from said fuse element after said fuse element is pre-charged, to obtain readout data, and latching the readout data.

3. A device according to claim 1, wherein said function control section comprises a plurality of fuse circuits storing function control data corresponding to a plurality of functions including a redundancy function, a trimming function, a write-protect function, and a test disable function, and a plurality of fuse control circuits for respectively controlling said fuse circuits.

4. A device according to claim 3, wherein said function control section comprises a fuse selection section for selecting all said plurality of fuse control circuits to read out the function control data from all said plurality of fuse circuits in response to a power-on operation.

5. A device according to claim 3, wherein said function control section comprises a fuse selection section for selecting at least one of said fuse control circuits to read out function control data from at least one of said fuse circuits in response to selection of a predetermined function.

6. A device according to claim 3, wherein each of said fuse circuits comprises a fuse element including MOS transistor having a stacked gate structure and storing function control data, and a fuse element control circuit for pre-charging said fuse element, reading out data from said fuse element after said fuse element is precharged, to obtain readout data, and latching the readout data.

7. A device according to claim 1, wherein said function control section keeps said fuse circuit in an inhibit state after the function control data is latched.

8. A device according to claim 1, wherein said function control section comprises a power-on reset circuit for generating a power-on reset signal in response to a power-on operation, and a fuse latch trigger circuit for outputting a pre-charge signal, a readout signal, and a latch end signal in response to the power-on reset signal, and executes the fuse sequence in response to the signals.

9. A device according to claim 8, further comprising an input control circuit for inhibiting reception of the power-on reset signal for a predetermined period of time in response to one of the pre-charge signal, the readout signal, and the latch end signal, said input control circuit being connected to a front stage of said fuse latch trigger circuit.

10. A device according to claim 9, wherein said input control circuit comprises a pulse generating circuit for generating a pulse signal having a predetermined width corresponding to the predetermined period of time.

11. A semiconductor memory device comprising:

a memory cell array;

a memory control section which controls reading/writing data with respect to said memory cell array;

a sequence control section for controlling a sequence operation for realizing a function of said memory control section; and

a function control section for controlling a read/write of function control data used by said sequence control section to perform the sequence operation, and executing a read of data from said function control section at the time of power-on and selection of a predetermined function.

12. A device according to claim 11, wherein said function control section comprises a fuse element including a MOS transistor having a stacked gate structure, said fuse element storing the function control data, and a fuse circuit including a fuse element control circuit for pre-charging said fuse element, reading out data from said fuse element after said fuse element is pre-charged, to obtain readout data, and latching the readout data.

13. A device according to claim 11, wherein said function control section comprises a plurality of fuse circuits storing function control data corresponding to a plurality of functions including a redundancy function, a trimming function, a write-protect function, and a test disable function, and a plurality of fuse control circuits for respectively controlling said fuse circuits.

14. A device according to claim 13, wherein said function control section comprises a fuse selection section for selecting all said plurality of fuse control circuits to read out the function control data from all said plurality of fuse circuits in response to a power-on operation.

15. A device according to claim 13, wherein said function control section comprises a fuse selection section for selecting at least one of said fuse control circuits to read out function control data from at least one of said fuse circuits in response to selection of a predetermined function.

16. A device according to claim 13, wherein each of said fuse circuits comprises a fuse element including a MOS transistor having a stacked gate structure, said fuse element storing function control data, and a fuse element control circuit for pre-charging said fuse element, reading out data from said fuse element after said fuse clement is pre-charged, to obtain readout data, and latching the readout data.

17. A device according to claim 16, wherein said function control section keeps said fuse circuit in an inhibit state after the function control data is latched.

18. A device according to claim 11, wherein said function control section comprises a power-on reset circuit for generating a power-on reset signal in response to a power-on operation, and a fuse latch trigger circuit for outputting a pre-charge signal, a readout signal, and a latch end signal in response to the power-on reset signal, and executes the sequence operation in response to the signals.

19. A device according to claim 18, further comprising an input control circuit for inhibiting reception of the power-on reset signal for a predetermined period of time in response to one of the pre-charge signal, the readout signal, and the latch end signal, said input control circuit being connected to a front stage of said fuse latch trigger circuit.

20. A semiconductor memory device comprising:

a MOS transistor used as a fuse element for storing function control data and having a drain and a stacked gate structure in which a floating gate and a control gate are stacked on each other; and

a sequence control circuit for pre-charging a drain of said MOS transistor upon reception of a predetermined control signal, reading out data from said MOS transistor after the drain of said MOS transistor is pre-charged, to obtain readout data, and latching the readout data, said sequence control circuit including a pre-charge circuit for pre-charging the drain of said MOS transistor at a predetermined timing for a predetermined period of time, a read circuit for reading out the function control data from said MOS transistor at a predetermined timing, a latch circuit for latching the data read out by said read circuit, and a fuse control circuit for sequentially generating a pre-charge signal for driving said pre-charge circuit, a readout control signal for driving said read circuit, and a latch signal for driving said latch circuit.

26. A device according to claim 20, wherein said sequence control circuit further comprises a write circuit for supplying a write current from a write voltage node to a drain of said MOS transistor when data is to be written therein.

27. A device according to claim 20, wherein the drain of said MOS transistor is controlled in a potential floating state after data is readout therefrom and latched.

21. A semiconductor memory device comprising:

a MOS transistor used as a fuse element for storing function control data and having a stacked gate structure in which a floating gate and a control gate are stacked on each other; and

a sequence control circuit for pre-charging a drain of said MOS transistor upon reception of a predetermined control signal, reading out data from said MOS transistor after the drain of said MOS transistor is pre-charged, to obtain readout data, and latching the readout data, said sequence control circuit including a plurality of MOS transistors, a plurality of pre-charge circuits corresponding to said MOS transistors, a plurality of read circuits, a plurality of latch circuits, a plurality of fuse control circuits, a fuse selection circuit for generating a fuse selection signal for selecting one of said plurality of fuse control circuits in accordance with logic of external signals, and a fuse latch trigger circuit which is commonly arranged for said plurality of fuse control circuits, outputs a latch trigger signal upon reception of the predetermined control signal, and commonly supplies the latch trigger signal to said plurality of fuse control circuits, and wherein one of said fuse control circuits which is selected by the fuse selection signal generates a pre-charge signal for driving said pre-charge circuits, a readout control signal for driving said read circuits, and a latch signal for driving said latch circuits upon reception of the latch trigger signal.

22. A device according to claim 21, which further comprises a power-on reset circuit for generating a power-on reset signal at power-on, and a verify circuit for performing verify read with respect to some MOS transistors, of said plurality of MOS transistors as fuse elements, in which data have been rewritten, and the power-on reset signal and a verify end signal are input as control signals to said fuse latch trigger circuit.

23. A device according to claim 22, wherein said fuse selection circuit selects all said plurality of fuse control circuits at power-on, and generates a fuse selection signal for selecting/controlling some corresponding fuse control circuits, of said plurality of fuse control circuits, after data in said some MOS transistors as fuse elements are rewritten.

24. A device according to claim 21, wherein said fuse latch trigger circuit comprises an input control circuit for generating the latch trigger signal in response to a falling edge of a power-on reset signal as a trigger, which is input from said power-on reset circuit, and controlling to inhibit reception of the power-on reset signal during at least the duration of the latch trigger signal.

25. A device according to claim 21, wherein said fuse latch trigger circuit comprises a pulse generating circuit for generating a pulse signal having a predetermined width in response to a falling edge of a power-on reset signal as a trigger, which is input from said power-on reset circuit, and controlling to inhibit reception of the power-on reset signal during the duration of the pulse signal.