Apparatus for processing two-dimensional information

• US 6,088,490 A
• Filed: 03/25/1998
• Issued: 07/11/2000
• Est. Priority Date: 03/28/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Hiroshima University
• Inventors: Iwata, Atsushi, Nagata, Makoto
• Primary Examiner(s): Couso, Jose L.
• Assistant Examiner(s): Do, Anh Hong
• Application Number:
  US09/047,378
• Time in Patent Office: 839 Days
• Field of Search: 382/312, 382/317, 708/7, 712/11, 706/26
• US Class Current: 382/312
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A two-dimensional information processing apparatus comprises a plurality of unit cell circuits arranged in a tow-dimensional matrix and each including a detector for detecting information as predetermined part of two-dimensional information, a storage circuit for storing the information detected by the detector, and a signal processing circuit for generating a pulse width modulation signal which has a pulse width corresponding to the information detected or stored, a plurality of address lines extending in a direction of columns of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the columns, a plurality of bus lines extending in a direction of rows of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the rows, means for selecting at least one of the address lines and supplying, through the selected address line, a control signal for generating a pulse width modulation signal to those unit cell circuits which are included in the selected bus line, and means for selecting at least one of the bus lines and reading, through the selected bus line, at least one pulse width modulation signal. The control signal includes a ramp signal, and the pulse modulation signal rises when the voltage of the ramp signal starts to increase, and falls when the voltage of the ramp signal is identical to a voltage determined on the basis of the information detected by the detector.

Claims

1. A two-dimensional information processing apparatus comprising:

a plurality of unit cell circuits arranged in a tow-dimensional matrix and each including a detector for detecting information as predetermined part of two-dimensional information, a storage circuit for storing information detected by the detector, and a signal processing circuit for generating a pulse width modulation signal which has a pulse width corresponding to the information detected or stored;

a plurality of address lines extending in a direction of columns of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the columns;

a plurality of bus lines extending in a direction of rows of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the rows;

means for selecting at least one of the address lines and supplying those unit cell circuits which are included in the selected address line, with a control signal for causing those unit cell circuits to generate pulse width modulation signals; and

means for selecting at least one of the bus lines and reading, through the selected bus line, at least one of the pulse width modulation signals.

2. The apparatus according to claim 1, wherein the control signal includes a ramp signal, and the pulse modulation signal rises when the voltage of the ramp signal starts to increase, and falls when the voltage of the ramp signal is identical to a voltage determined on the basis of the information detected by the detector.

3. The apparatus according to claim 1, wherein the two-dimensional information is optical information, and the detector is a photodetector.

4. The apparatus according to claim 2, wherein the two-dimensional information is optical information, and the detector is a photodetector.

5. The apparatus according to claim 1, wherein the means for selecting at least one of the address lines includes means for designating any voluntary one of the address lines, and the reading means includes means for reading, through corresponding at least one bus line, a pulse width modulation signal generated in at least one of the unit cell circuits which are connected to the designated address line.

6. The apparatus according to claims 2, wherein the means for selecting at least one of the address lines includes means for designating any voluntary one of the address lines, and the reading means includes means for reading, through corresponding at least one bus line, a pulse width modulation signal generated in at least one of the unit cell circuits which are connected to the designated first bus line.

7. The apparatus according to claim 1, wherein the means for selecting at least one of the address lines includes means for sequentially scanning the address lines for selection thereof and sequentially supplying a ramp signal to the selected address lines, and the reading means includes means for sequentially reading generated pulse modulation signals through the at least one bus line.

8. The apparatus according to claim 2, wherein the means for selecting at least one of the address lines includes means for sequentially scanning the address lines for selection thereof and sequentially supplying a ramp signal to the selected address lines, and the reading means includes means for sequentially reading generated pulse modulation signals through the at least one bus line.

9. The apparatus according to claim 1, wherein the signal processing circuit has an output circuit, as a current supply driving circuit, for outputting the pulse width modulation signal, the means for selecting at least one of the address lines includes means for simultaneously selecting some of the address lines and supplying them with a ramp signal, and the reading means includes means for adding together currents in each of the bus lines, which currents indicate pulse width modulation signals output from row-directional unit cell circuits, and obtaining the sum of information items represented by pulse width modulation signals output in the form of charges from the row-directional unit cell circuits.

10. The apparatus according to claim 2, wherein the signal processing circuit has an output circuit, as a current supply driving circuit, for outputting the pulse width modulation signal, the means for selecting at least one of the address lines includes means for simultaneously selecting some of the address lines and supplying them with a ramp signal, and the reading means includes means for adding together currents in each of the bus lines, which currents indicate pulse width modulation signals output from row-directional unit cell circuits, and obtaining the sum of information items represented by pulse width modulation signals output in the form of charges from the row-directional unit cell circuits.

11. The apparatus according to claim 9, wherein the ramp signal supplied to the address lines has a waveform with an inclination corresponding to a predetermined coefficient, in order to output, as the pulse width modulation signal, a value obtained by multiplying the detected information amount by the predetermined coefficient.

12. The apparatus according to claim 11, wherein when the predetermined coefficient has a positive polarity and a negative polarity, the reading means includes means for obtaining the sum of outputs which are multiplied by the positive coefficient and the sum of outputs which are multiplied by the negative coefficient, and calculating the differences between the sums.

13. The apparatus according to claim 11, wherein the bus lines each include a positive polarity bus line for receiving outputs when the predetermined coefficient is positive, and a negative polarity bus line for receiving outputs when the predetermined coefficient is negative, and the reading means includes means for calculating the difference between the sum of the outputs received in the positive polarity bus line and the sum of the outputs received in the negative polarity bus line.

14. The apparatus according to claim 1, wherein in order to detect whether or not the two-dimensional information contains a pattern edge, and to detect the position of the pattern edge, each of the address line and bus line selecting means selects each pair of adjacent ones of the unit cell circuits, and the reading means calculates the difference in pulse width between pulse width modulation signals output from the pair of adjacent unit cell circuits, and compares the difference with a threshold value.

15. The apparatus according to claim 2, wherein in order to detect whether or not the two-dimensional information contains a pattern edge, and to detect the position of the pattern edge, each of the address line and bus line selecting means selects each pair of adjacent ones of the unit cell circuits, and the reading means calculates the difference in pulse width between pulse width modulation signals output from the pair of adjacent unit cell circuits, and compares the difference with a threshold value.