High resolution frequency calibrator for sleep mode clock in wireless communications mobile station

• US 6,088,602 A
• Filed: 03/27/1998
• Issued: 07/11/2000
• Est. Priority Date: 03/27/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Banister, Brian C.
• Primary Examiner(s): Bost, Dwayne D.
• Assistant Examiner(s): CONTEE, JOY KIMBERLY
• Application Number:
  US09/049,962
• Time in Patent Office: 837 Days
• Field of Search: 455/574, 455/38.3, 455/343, 455/422, 455/403, 455/550, 370/311, 370/335
• US Class Current: 455/574
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention concerns a high resolution calibrator for a sleep mode clock of a mobile station in a wireless communications system. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and circuitry clocked by it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic. In a preferred version, the calibrator includes two counters: a first counter which counts up to S*T0 cycles of the super chip rate clock through one data frame, then rolls over to zero, and a second counter which counts cycles of the sleep mode clock. Also included are three registers: a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time; a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period; and a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period. Wake up time is determined using a relative frequency which is calculated from values stored in the above registers.

Claims

1. A high resolution calibrator for calibrating a sleep mode clock in a wireless communications mobile station to a chip rate clock operating at a chip rate and which can be turned off during sleep mode, wherein data is segmented into frames having a duration T0, and the mobile station includes a super chip rate clock which operates at a frequency S which is N times the chip rate, and a frame counter which contains a value FRMS at the end of a calibration period, said calibrator comprising:

a first counter which counts T0*S cycles of the super chip rate clock through one data frame, then rolls over to zero;

a second counter which counts cycles of the sleep mode clock;

a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time;

a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period;

a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period,

wherein wake up time is calculated using a relative frequency which is equal to

space="preserve" listing-type="equation">[SYSTIME2-SYSTIME1+(T0*S)(FRMS)]/CNTSLP.

2. The calibrator according to claim 1 wherein said sleep mode clock runs between 31 kHz and 33 kHz.

3. The calibrator according to claim 1 wherein storage of SYSTIME1 and SYSTIME2 is synchronized to the sleep mode clock.

4. The calibrator according to claim 1 wherein wake up can be initiated by a user before a sleep period ends.

5. The calibrator according to claim 1 wherein said calibrator compensates for frequency variations in the sleep mode clock, wherein the frequency variations result from the sleep mode clock operating at a different frequency during sleep mode than during a calibration period.

6. The calibrator according to claim 5 wherein the calibrator compensates for frequency variations by modifying the relative frequency by a factor.

7. A wireless communications mobile station wherein data is segmented into frames having a duration T0, said mobile station comprising:

a. transmitting circuitry which transmits as spread spectrum signals data provided by a user;

b. receiving circuitry which receives spread spectrum signals and converts the signals into a form intelligible to the user;

c. PN sequence generator circuitry operationally connected to the transmitting circuitry and the receiving circuitry;

d. a chip rate clock, operating at a chip rate, which clocks the PN sequence generator circuitry and which can be turned off during sleep mode;

e. sleep mode logic circuitry;

f. a sleep mode clock which clocks the sleep mode logic circuitry;

g. a super chip rate clock which operates at a frequency S which is N times the chip rate;

h. a frame counter which contains a value FRMS at the end of a calibration period; and

i. a calibrator for calibrating said sleep mode clock to the chip rate clock before entry into sleep mode, said calibrator comprising;

a first counter, clocked by the super chip rate clock, which counts T0*S cycles of the super chip rate clock through one data frame, then rolls over to zero;

a second counter which counts cycles of the sleep mode clock;

a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time;

a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period;

a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period,

wherein wake up time is calculated using a relative frequency which is equal to

space="preserve" listing-type="equation">[SYSTIME2-SYSTIME1+(T0*S)(FRMS)]/CNTSLP.

8. The wireless communications mobile station according to claim 7 wherein said sleep mode clock runs between 31 kHz and 33 kHz.

9. The wireless communications mobile station according to claim 7 wherein storage of SYSTIME1 and SYSTIME2 is synchronized to the sleep mode clock.

10. The wireless communications mobile station according to claim 7 wherein wake up can be initiated by a user before a sleep period ends.

11. The wireless communications mobile station according to claim 7 wherein said calibrator compensates for frequency variations in the sleep mode clock, wherein the frequency variations result from the sleep mode clock operating at a different frequency during sleep mode than during a calibration period.

12. The wireless communications mobile station according to claim 11 wherein the calibrator compensates for frequency variations by modifying the relative frequency by a factor.

13. A method for high resolution calibration of a sleep mode clock in a wireless communications mobile station to a chip rate clock operating at a chip rate and which can be turned off during sleep mode, wherein data is segmented into frames having a duration T0, and the mobile station includes a super chip rate clock which operates at a frequency S which is N times the chip rate, and a frame counter which contains a value FRMS at the end of a calibration period, said method comprising the steps of:

counting in a first counter T0*S cycles of the super chip rate clock through each data frame;

counting in a second counter cycles of the sleep mode clock;

storing in a first register a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time;

storing in a second register a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period;

storing in a third register a third value SYSTIME2 which is input from the first counter at the end of a calibration period,

determining wake up time using a relative frequency which is equal to

space="preserve" listing-type="equation">[SYSTIME2-SYSTIME1+(T0*S)(FRMS)]/CNTSLP.

14. The method according to claim 13 wherein wake up can be initiated by a user before a sleep period ends.

15. The method according to claim 13 wherein the method compensates for frequency variations in the sleep mode clock, wherein the frequency variations result from the sleep mode clock operating at a different frequency during sleep mode than during a calibration period.

16. The method according to claim 15 wherein the method compensates for frequency variations by modifying the relative frequency by a factor.

17. A wireless communications system comprising:

a. a mobile station,

b. a base station subsystem which controls the radio link with the mobile station, and

c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following;

(1) transmitting circuitry which transmits as spread spectrum signals data provided by a user;

(2) receiving circuitry which receives spread spectrum signals and converts the signals into a form intelligible to the user;

(3) PN sequence generator circuitry operationally connected to the transmitting circuitry and the receiving circuitry;

(4) a chip rate clock, operating at a chip rate, which clocks the PN sequence generator circuitry and which can be turned off during sleep mode;

(5) sleep mode logic circuitry;

(6) a sleep mode clock which clocks the sleep mode logic circuitry;

(7) a super chip rate clock which operates at a frequency S which is N times the chip rate;

(8) a frame counter which contains a value FRMS at the end of a calibration period; and

(9) a calibrator for calibrating said sleep mode clock to the chip rate clock before entry into sleep mode, said calibrator comprising;

a first counter, clocked by the super chip rate clock, which counts T0*S cycles of the super chip rate clock through one data frame, then rolls over to zero;

a second counter which counts cycles of the sleep mode clock;

a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time;

a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period;

a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period,

wherein wake up time is calculated using a relative frequency which is equal to

space="preserve" listing-type="equation">[SYSTIME2-SYSTIME1+(T0*S)(FRMS)]/CNTSLP.

18. The wireless communications system according to claim 17 wherein storage of SYSTIME1 and SYSTIME2 is synchronized to the sleep mode clock.

19. The wireless communications system according to claim 17 wherein said sleep mode clock runs between 31 kHz and 33 kHz.

20. The wireless communications system according to claim 17 wherein said sleep mode clock runs between 32 kHz minus 50 ppm and 32 kHz plus 50 ppm.

21. The wireless communications system according to claim 17 wherein said sleep mode clock runs at about 32 kHz.

22. The wireless communications system according to claim 17 wherein wake up can be initiated by a user before a sleep period ends.

23. The wireless communications system according to claim 17 wherein said calibrator compensates for frequency variations in the sleep mode clock, wherein the frequency variations result from the sleep mode clock operating at a different frequency during sleep mode than during a calibration period.

24. The wireless communications system according to claim 23 wherein the calibrator compensates for frequency variations by modifying the relative frequency by a factor.

25. The wireless communications system according to claim 22 wherein the first counter is reset, and the first register is loaded from the second counter, upon wake up synchronous to the first sleep mode clock cycle after wake up is initiated.