Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
First Claim
1. A method of maintaining coherent shared memory within a multiprocessor system including a plurality of memory devices sharing a shared memory interval, comprising the steps of:
- sending a first request packet from a requesting memory device directing a responding memory device having a copy of the shared memory interval to perform an action on the copy;
returning the first request packet to the requesting memory device if the copy is in a transient state such that the copy is the subject of an outstanding transaction; and
resending the request packet to the responding memory device, wherein the step of resending is performed only after ensuring that the conditions under which the original request was generated still dictate that the request should be performed.
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Abstract
A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.
50 Citations
15 Claims
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1. A method of maintaining coherent shared memory within a multiprocessor system including a plurality of memory devices sharing a shared memory interval, comprising the steps of:
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sending a first request packet from a requesting memory device directing a responding memory device having a copy of the shared memory interval to perform an action on the copy; returning the first request packet to the requesting memory device if the copy is in a transient state such that the copy is the subject of an outstanding transaction; and resending the request packet to the responding memory device, wherein the step of resending is performed only after ensuring that the conditions under which the original request was generated still dictate that the request should be performed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A data processing system, comprising:
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a first memory device containing a shared memory block, wherein the first memory device returns to sender a received request packet that requests an operation involving a memory block in a transient state; and a second memory device in communication with the first memory device that sends a request packet directing the first memory device to perform an operation on the shared memory block, if the request packet is returned indicating the shared memory block is in a transient state, the second memory device resends the request packet to the first memory device, wherein the second device resends the request packet only if the conditions requiring the operation are still valid. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification
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- Resources
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsBaldus, Donald Francis, Duffield, Nancy Joan, Hoover, Russell Dean, Willis, John Christopher, Ziegler, Frederick Jacob
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Primary Examiner(s)Thai, Tuan V.
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Application NumberUS08/174,648Time in Patent Office2,387 DaysField of Search395/471, 395/472, 395/474, 395/477, 395/479, 395/446, 711/3, 711/117, 711/118, 711/119, 711/130, 711/141, 711/154, 711/147US Class Current711/141CPC Class CodesG06F 12/0813 with a network or matrix co...G06F 12/0815 Cache consistency protocols
