Data access controller and data access control method

• US 6,088,775 A
• Filed: 10/20/1997
• Issued: 07/11/2000
• Est. Priority Date: 10/22/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Inoue, Koji, Todo, Hirofumi, Shigenobu, Masahiro
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/954,300
• Time in Patent Office: 995 Days
• Field of Search: 711/118, 711/154, 711/157, 711/167, 710/52, 710/53
• US Class Current: 711/167
• CPC Class Codes: G11B 20/1809 by interleaving

Abstract

A data access controller has an SRAM adapted to hold two ECC blocks so that the SRAM is used efficiently for multiple kinds of processes. At playback of data, writing of ECC block A from a demodulator and an ECC process for ECC block B begin simultaneously. When the ECC process ends, release of the ECC block B to the outside begins. When the writing of ECC block A ends, the ECC process for the ECC block A begins and, at the same time, writing of ECC block B from the demodulator begins.

Claims

1. A data access controller comprising:

means of memorizing data;

means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes; and

means of providing the addresses on a time-slice basis for said memory means,

wherein said memory means is accessed for data reading and writing at addresses given on a time-slice basis by said address providing means, and said address generation means generates addresses such that reading-out of data from a certain memory address by a certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process of said multiple kinds of processes, wherein said multiple kinds of processes include a data modulation process, a data demodulation process, an ECC encoding process for appending C1 and C2 parities to data, and an error detection/correction process which is based on the C1 and C2 parities.

2. A data access controller comprising:

means of memorizing data;

means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes; and

means of providing the addresses on a time-slice basis for said memory means,

wherein said memory means is accessed for data reading and writing at addresses given on a time-slice basis by said address providing means, and said address generation means generates addresses such that reading-out of data from a certain memory address by certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by certain one other process, and wherein said multiple kinds of processes include a data modulation process, data demodulation process, data input/output process, ECC encoding process for appending C1 and C2 parities to data, and error detection/correction process which is based on the C1 and C2 parities, and wherein said data modulation process and data demodulation process which transact data with said memory means at a constant transfer rate are carried out on a priority basis over other processes that are carried out in time gaps of the modulation and demodulation processes.

3. A data access controller comprising:

means of memorizing data;

means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes; and

means of providing the addresses on a time-slice basis for said memory means,

wherein said memory means is accessed for data reading and writing at addresses given on a time-slice basis by said address providing means, and said address generation means generates addresses such that reading-out of data from a certain memory address by certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by certain one other process, and wherein said address providing means provides addresses for a data modulation process and a data demodulation process in correspondence to an address map of ECC blocks.

4. A data access controller comprising:

means of memorizing data;

means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes; and

means of providing the addresses on a time-slice basis for said memory means,

wherein said memory means is accessed for data reading and writing at addresses given on a time-slice basis by said address providing means, and said address generation means generates addresses such that reading-out of data from a certain memory address by certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by certain one other process, and wherein said multiple kinds of processes include a data modulation process, data demodulation process, data input/output process, ECC encoding process for appending C1 and C2 parities to data, and error detection/correction process which is based on the C1 and C2 parities, and wherein said error detection/correction process which is implemented for data written in said memory means after said data demodulation process is carried out three times for each of the C1 and C2 parities.

5. A data access controller comprising:

means of memorizing data;

means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes;

means of providing the addresses on a time-slice basis for said memory means; and

means of appending C1 and C2 parities to data,

wherein the memory means writes and reads out data at addresses given on a time-slice basis by said address providing means, said parity appending means distributes the C2 parities so that their memory addresses scatter, and said address generation means generates different addresses for the case of the ECC encoding process in which the C1 and C2 parities are appended to data and for the case of the data modulation process or data demodulation process.

6. A data access controller according to claim 5, wherein said address generation means generates addresses for making access to the C1 and C2 parities at once at the end of process in the case of the ECC encoding process in which the C1 and C2 parities are appended to data or the ECC decoding process in which data undergoes error detection/correction, or generates addresses for making access to data and the C1 and C2 parities in correspondence to the address map of ECC blocks in the case of the data modulation process or data demodulation process.

7. A memory controller for controlling a memory for an error correction coding/decoding process, comprising:

a read address generator for generating a read address;

a write address generator for generating a write address;

a read/write address generator for generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

a selector for selecting an output from one of the read address generator, the write address generator and the read/write address generator; and

a controller for controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written, wherein said data modulation process and said data demodulation process each which transact data with said memory at a constant transfer rate are carried out on a priority basis over other processes that are carried out in time gaps of the modulation and demodulation processes.

8. A memory controller for controlling a memory for an error correction coding/decoding process, comprising:

a read address generator for generating a read address;

a write address generator for generating a write address;

a read/write address generator for generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

a selector for selecting an output from one of the read address generator, the write address generator and the read/write address generator; and

a controller for controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written, wherein said read/write address generator provides addresses for said data modulation process and said data demodulation process in correspondence with an address map of ECC blocks.

9. A memory controller for controlling a memory for an error correction coding/decoding process, comprising:

a read address generator for generating a read address;

a write address generator for generating a write address;

a read/write address generator for generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

a selector for selecting an output from one of the read address generator, the write address generator and the read/write address generator; and

a controller for controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written, wherein said error correction coding/decoding process which is implemented for data written in said memory after said data demodulation process is carried out three times for each of C1 and C2 parities.

10. A method of controlling data access to/from a memory for an error correction coding/decoding process, comprising:

generating a read address;

generating a write address;

generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

selecting an output from one of the read address generator, the write address generator and the read/write address generator;

controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written; and

prioritizing said data modulation process and said data demodulation process, each which transact data with said memory at a constant transfer rate, over other processes that are carried out in time gaps of the modulation and demodulation processes.

11. A method of controlling data access to/from a memory for an error correction coding/decoding process, comprising:

generating a read address;

generating a write address;

generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

selecting an output from one of the read address generator, the write address generator and the read/write address generator; and

controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written, wherein said read/write address generating step includes providing addresses for said data modulation process and said data demodulation process in correspondence with an address map of ECC blocks.

12. A method of controlling data access to/from a memory for an error correction coding/decoding process, comprising:

generating a read address;

generating a write address;

generating a read/write address in order to write data to the memory in a demodulation process and to read data from the memory in a modulation process;

selecting an output from one of the read address generator, the write address generator and the read/write address generator; and

controlling address generation timing, wherein said read address is generated a predetermined time before said write address is generated such that data corresponding to said read address is read out before data corresponding to said write address is written, wherein said error correction coding/decoding process which is implemented for data written in said memory after said data demodulation process is carried out three times for each of C1 and C2 parities.