Computer system with low power mode invoked by halt instruction

• US 6,088,807 A
• Filed: 12/09/1996
• Issued: 07/11/2000
• Est. Priority Date: 03/27/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bluhm, Mark, Maher, Robert, Garibay, Raul A. Jr., Herubin, Margaret R.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/777,772
• Time in Patent Office: 1,310 Days
• Field of Search: 395/750.04, 713/322, 713/324, 713/330
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

Claims

1. A programmed computer system including a processor coupled to external logic, the processor executing programmed instructions, the external logic including external interrupt logic that generates interrupts for input to the processor, comprising:

(a) the processor including a plurality of subcircuits and clock generator circuitry coupled to supply clock signals to the plurality of subcircuits;

(b) the plurality of subcircuits including a pipeline subcircuit to execute the programmed instructions, at least one of which is a halt instruction, and an interrupt handling subcircuit to handle interrupts generated by the external interrupt logic;

(c) in response to the pipeline subcircuit executing the halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals at least to the pipeline subcircuit but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped;

(d) in response to an interrupt generated by the external interrupt logic when the clock generator circuitry is not supplying clock signals to the pipeline subcircuit, the interrupt handling subcircuit causes the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

2. The programmed computer system of claim 1, wherein executing the halt instruction and subsequently stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit is accomplished in a number of clock cycles that depends on the programmed instructions being processed by the pipeline subcircuit when the halt instruction is executed.

3. The programmed computer system of claim 1, further comprising a Read Only Memory containing a BIOS, the halt instruction being stored by the BIOS.

4. A computer system comprising:

(a) a processor having a plurality of subcircuits including an interrupt handler subcircuit to handle externally generated interrupts and a pipeline subcircuit to execute program instructions, and further having clock generator circuitry coupled to selectively supply clock signals to the plurality of subcircuits;

(b) logic circuitry external to the processor which receives signals from and provides interrupts to the processor; and

(c) a memory external to the processor for storing instructions for use by the processor, at least one of those instructions being a halt instruction;

wherein

(d) the processor, in response to the pipeline subcircuit executing the halt instruction, (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit but not to the interrupt handling subcircuit, thereby placing the processor into a low power mode, and (ii) generates a signal to the external logic circuitry indicating that the processor is entering the low power mode of operation; and

(e) in response to an interrupt generated by the external logic circuitry when the processor is in low power mode, the interrupt handling subcircuit enables the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

5. The computer system of claim 4, wherein executing the halt instruction and subsequently stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit is accomplished in a number of clock cycles that depends on the programmed instructions being processed by the pipeline subcircuit when the halt instruction is executed.

6. The computer system of claim 4, further comprising a Read Only Memory containing a BIOS, the halt instruction being stored by the BIOS.

7. A method of invoking a low power operational mode used in a programmed computer system that includes a processor coupled to external logic, the processor executing programmed instructions at least one of which is a halt instruction, the external logic including external interrupt logic that generates interrupts for input to the processor, comprising the steps:

(a) supplying clock signals to a plurality of subcircuits in the processor, the plurality of subcircuits including a pipeline subcircuit to execute the programmed instructions and an interrupt handling subcircuit to handle interrupts generated by the external interrupt logic;

(b) executing in the pipeline subcircuit a halt instruction;

(c) in response to the pipeline subcircuit executing the halt instruction, (i) stopping the clock signals at least to the pipeline subcircuit but not to the interrupt handling subcircuit, and (ii) generating an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, such that the processor enters a low power mode;

(d) in response to an interrupt generated by the external interrupt logic when the processor is in the low power mode, handling such interrupt in the interrupt handling subcircuit so as to resume supplying clock signals to the pipeline subcircuit.

8. The method of invoking a low power operational mode of claim 7, wherein the steps of executing the halt instruction and subsequently stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit are accomplished in a number of clock cycles that depends on the programmed instructions being processed by the pipeline subcircuit when the halt instruction is executed.

9. The method of invoking a low power operational mode of claim 7, wherein the computer system includes a Read Only Memory containing a BIOS, the halt instruction being stored by the BIOS.