Byte synchronization system and method using an error correcting code

• US 6,089,749 A
• Filed: 07/08/1997
• Issued: 07/18/2000
• Est. Priority Date: 07/08/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blaum, Mario, Tang, Denny Duan-lee, Yasuda, Takeo
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/889,363
• Time in Patent Office: 1,106 Days
• Field of Search: 371/47.1, 371/48, 371/43.7, 371/46, 371/43.6, 375/357
• US Class Current: 714/798
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/39 Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A byte synchronization detection system and method in which a vector subtractor circuit determines an error vector between a current read data pattern and a synchronization bit pattern, and an offset adder circuit determines a Hamming Distance of the next read data pattern by adding the difference between the Hamming Distance from current error vector to the synchronization bit pattern and the Hamming Distance from the next error vector to the synchronization bit pattern. The Hamming Distance is determined by selected elements of the error vector which are the output from the vector subtractor circuit. The offset adder circuit determines a difference between the Hamming Distance of the current read data pattern and of the next read data pattern. The synchronization bit pattern is between 16 and 18 bits in length, inclusive. This approach reduces the probability of synchronization failure and/or mis-synchronization about 4 orders of magnitude over conventional approaches, while also reducing the length of the byte synchronization pattern to 16 bits.

Claims

1. A byte synchronization detection circuit comprising:

a vector subtractor circuit determining an error vector between a current read data pattern and a synchronization bit pattern; and

an offset adder circuit determining a distance of the next read data pattern by adding a difference between a Hamming Distance from a current error vector to the synchronization bit pattern and a Hamming Distance from a next error vector to the synchronization bit pattern using selected bits of the error vector determined by the vector subtractor circuit to a distance of the current read data pattern.

2. The byte synchronization detection circuit according to claim 1, wherein the offset adder circuit further determines a difference between the Hamming Distance of the current read data pattern to the synchronization bit pattern and a Hamming Distance of the next read data pattern to the synchronization bit pattern.

3. The byte synchronization detection circuit according to claim 2, wherein the vector subtractor circuit includes a shift register formed from a plurality of sequentially connected latches, each latch having an output polarity that corresponds to an exclusive-or'"'"'ed result of two adjacent synchronization bit patterns, the synchronization bit pattern formed from a predetermined sequence of first and second predetermined output polarities, and the output of the latches generates the error vector between the current read data pattern and the synchronization bit pattern.

4. The byte synchronization detection circuit according to claim 3, wherein the output polarity of each latch is a signal representing one of a "1" and a "0".

5. The byte synchronization detection circuit according to claim 3, wherein the synchronization bit pattern is between 16 and 18 bits in length, inclusive.

6. The byte synchronization detection circuit according to claim 5, wherein the synchronization bit pattern is 16 bits in length.

7. The byte synchronization detection circuit according to claim 3, wherein a probability of synchronization failure and mis-synchronization is about 1×

10^-9 at about 16 dB signal-to-noise ratio.

8. The byte synchronization detection circuit according to claim 7, wherein the probability of synchronization failure and mis-synchronization is about 1×

10^-16 at about 19 dB signal-to-noise ratio.

9. A method of byte synchronization, the method comprising the steps of:

determining an error vector between a current read data pattern and a synchronization bit pattern; and

determining the Hamming Distance of the next read data pattern by adding a difference of a Hamming Distance determined by using selected bits of the error vector to a Hamming Distance of the current read data pattern.

10. The method according to claim 9, further comprising the step of determining a difference between a Hamming Distance of the current read data pattern to the synchronization bit pattern and a Hamming Distance of the next read data pattern to the synchronization bit pattern.

11. The method according to claim 10, wherein the synchronization bit pattern is between 16 and 18 bits in length, inclusive.

12. The method according to claim 11, wherein the synchronization bit pattern is 16 bits in length.

13. The method according to claim 11, wherein a probability of synchronization failure and mis-synchronization is about 1×

10^-9 at about 16 dB signal-to-noise ratio.

14. The method according to claim 13, wherein the probability of synchronization failure and mis-synchronization is about 1×

10^-16 at about 19 dB signal-to-noise ratio.