Method to fabricate sharp tip of poly in split gate flash

• US 6,090,668 A
• Filed: 02/11/1999
• Issued: 07/18/2000
• Est. Priority Date: 02/11/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Jung-Ke, Lin, Chang-Song, Hsieh, Chia-Ta, Sung, Hung-Cheng, Kuo, Di-Son, Lin, Yai-Fen
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/248,725
• Time in Patent Office: 523 Days
• Field of Search: 438/257, 438/264, 438/266, 438/267, 438/304, 438/593, 438/594, 438/595, 438/596
• US Class Current: 438/266
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Claims

1. A method of forming a sharp poly tip to improve erase speed in a split-gate flash memory cell comprising the steps of:

providing a silicon substrate having a plurality of active and field regions defined;

forming a gate oxide layer over said substrate;

forming a first polysilicon layer over said gate oxide layer;

forming a layer of nitride over said first polysilicon layer;

forming and patterning a first photoresist layer to form a photoresist mask with a pattern corresponding to the floating gate of said split-gate flash memory cell;

etching said layer of nitride through said photoresist mask to form openings in said layer of nitride and to expose portions of said first polysilicon layer corresponding to said floating gate pattern;

performing a high pressure etch to form a recess with a sloped profile in said first polysilicon layer;

removing said first photoresist layer;

depositing a top-oxide layer into said recess having said sloped profile wherein said top-oxide overfills said recess extending into said opening in said layer of nitride;

partially removing said top-oxide from said opening in said layer of nitride;

removing said layer of nitride;

performing an etch using said top-oxide as a hard mask to etch portions of said first polysilicon layer not covered by said top-oxide to form floating gate underlying said top-oxide;

forming an interpoly oxide over said top-oxide layer;

depositing a second polysilicon layer over said interpoly oxide; and

patterning said second polysilicon layer with a second photoresist mask having control gate pattern to form a control gate to complete the forming of said split-gate flash memory cell having said sharp poly tip to improve erase speed of said memory.

2. The method of claim 1, wherein said gate oxide layer has a thickness between about 90 to 100 angstroms (Å

).

3. The method of claim 1, wherein said forming a first polysilicon layer is accomplished with silicon source SiH₄ using LPCVD at a temperature between about 530 to 610°

C.

4. The method of claim 1, wherein said first polysilicon layer has a thickness between about 1100 to 1300 angstroms (Å

).

5. The method of claim 1, wherein said forming a layer of nitride is accomplished with LPCVD at a temperature between about 730°

C. to 830°

C. by reacting dichlorosilane (SiCl₂ H₂)with ammonia (NH₃).

6. The method of claim 4, wherein the thickness of said layer of nitride is between about 750 to 850 Å

.

7. The method of claim 1, wherein said etching said layer of nitride is accomplished with etch recipe comprising gases Ar, CHF₃, C₄ F₈.

8. The method of claim 1, wherein said forming a recess having a sloped profile in said first polysilicon layer is accomplished with a recipe comprising gases HBr and He at flow rates between about 150 to 250 and 50 to 150 sccm, respectively, and at a pressure between about 60 to 120 mTorr.

9. The method of claim 1, wherein said recess in said first polysilicon layer has a depth between about 700 to 800 Å

.

10. The method of claim 1, wherein the slope of said sloped profile is between about 5 to 25 degrees from the vertical.

11. The method of claim 1, wherein said depositing said top-oxide into said recess is accomplished by CVD method.

12. The method of claim 11, wherein the thickness of said top-oxide is between about 1400 to 1600 Å

.

13. The method of claim 1, wherein said etch using said top-oxide as a hard mask to etch portions of said first polysilicon layer is accomplished with a recipe comprising gases HBr and Cl₂.

14. The method of claim 1, wherein said interpoly oxide is oxynitride with a thickness between about 150 to 250 Å

.

15. The method of claim 1, wherein said depositing a second polysilicon layer over said interpoly oxide is accomplished with silicon source SiH₄ using LPCVD at a temperature between about 550 to 620°

C.

16. The method of claim 1, wherein said second polysilicon layer to form a control gate has a thickness between about 1000 to 1300 Å

.