Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors

• US 6,090,693 A
• Filed: 08/16/1999
• Issued: 07/18/2000
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kao, David, Gonzalez, Fernando
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/375,102
• Time in Patent Office: 337 Days
• Field of Search: 438/304, 438/592, 438/596, 438/305, 257/366
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistors are used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors, using the gate spacers in a conventional manner, and/or as conventional transistors.

Claims

1. A method of making a transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure;

forming a secondary oxide layer on said gate structure;

forming a conductive spacer around said gate structure on said secondary oxide layer;

removing said conductive spacer from a portion of said gate structure;

forming a first contact to said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer.

2. A method of making a transistor structure comprising the steps of:

forming a gate on a first oxide layer on a semiconductor structure;

forming a conductive spacer connection support on said first oxide layer on said semiconductor structure but separated from said gate;

forming a secondary oxide layer on said gate and said conductive spacer connection support;

forming a conductive spacer on said gate and said conductive spacer connection support on said secondary oxide layer;

removing said conductive spacer from a portion of said gate;

forming a first contact to said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer at said conductive spacer connection support.

3. A method of making a dual gate transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure to define a first gate;

forming a secondary oxide layer over said gate structure;

forming a conductive spacer around said gate structure on said secondary oxide layer to define a second gate;

removing said conductive spacer from a portion of said gate structure;

forming a first contact to said first gate at said portion of said gate structure from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer.

4. A method of making a transistor structure comprising the steps of:

forming an actual gate on a first oxide layer on a semiconductor structure;

forming a pseudo gate on said first oxide layer on said semiconductor structure;

forming a secondary oxide layer over said actual gate and said pseudo gate;

forming a conductive spacer on said actual gate and said pseudo gate on said secondary oxide layer;

removing said conductive spacer from a portion of said actual gate;

forming a first contact to said actual gate at said portion of said actual gate from which said conductive spacer has been removed; and

forming a second contact to said conductive spacer at said pseudo gate.

5. A method of making an integrated circuit structure comprising the steps of:

forming gate structures on a first oxide layer on a semiconductor structure;

forming a secondary oxide layer on said gate structures;

forming conductive spacers around said gate structures;

utilizing said conductive spacers to form LDD transistor structures associated with a first number of said gate structures;

utilizing said conductive spacers to form transistor structures associated with a second number of said gate structures by performing the steps of;

removing said conductive spacer from portions of said second number of said gate structures;

forming first contacts to said second number of gate structures at said portions of said second number of gate structures from which said conductive spacer has been removed; and

forming second contacts to said conductive spacers.

6. A method of making a transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure;

forming a secondary oxide layer on said gate structure;

forming a conductive layer around said gate structure on said secondary oxide layer;

forming a nonconductive spacer over said conductive layer;

removing said conductive layer and said nonconductive spacer from a portion of said gate structure;

forming a first contact to said portion of said gate structure from which said conductive layer and nonconductive spacer have been removed; and

forming a second contact to said conductive layer.

7. A method of making a transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure;

forming a connection support on said first oxide layer on said semiconductor structure but separated from said gate structure;

forming a secondary oxide layer on said gate structure and said connection support;

forming a conductive layer around said gate structure and said connection support on said secondary oxide layer;

forming a nonconductive spacer over said conductive layer;

removing said nonconductive spacer from a portion of said gate structure;

removing said conductive layer from said portion of said gate structure;

forming a first contact to said portion of said gate structure from which said nonconductive spacer and said conductive layer have been removed; and

forming a second contact to said conductive layer at said connection support.

8. A method of making a transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure;

forming a secondary oxide layer on said gate structure;

forming a composite spacer around said gate structure on said secondary oxide layer, said composite spacer comprising a conductive layer formed over said gate structure and a nonconductive layer formed over said conductive layer;

removing said composite spacer from a portion of said gate structure;

forming a first contact to said portion of said gate structure from which said composite spacer has been removed; and

forming a second contact to said conductive layer of said composite spacer.

9. A method of making a multiple gate transistor structure comprising the steps of:

forming a gate structure on a first oxide layer on a semiconductor structure to define a first gate;

forming a secondary oxide layer over said gate structure;

forming a spacer on at least one side of said gate structure on said secondary oxide layer, at least a portion of said spacer adjacent to said secondary oxide layer being conductive and defining at least a second gate;

forming a first contact to said gate structure; and

forming at least a second contact to said conductive portion of said spacer.

10. A method for making a multiple gate transistor as claimed in claim 9 wherein said step of forming a spacer comprises the steps of:

forming a spacer on a first side of said gate structure to form a second gate;

forming a spacer on a second side of said gate structure to form a third gate separate from said second gate;

forming said second contact to said conductive portion of said spacer defining said second gate; and

said method further comprising the step of forming a third contact to said conductive portion of said spacer defining said third gate.

11. A method of making an integrated circuit structure comprising the steps of:

forming a first plurality of conventional transistors;

forming a second plurality of transistors by performing the steps of;

forming a gate structure on a first oxide layer on a semiconductor structure;

forming a secondary oxide layer on said gate structure;

forming a spacer on at least one side of said gate structure on said secondary oxide layer, at least a portion of said spacer adjacent to said secondary oxide layer being conductive and defining at least a second gate;

forming a first contact to said gate structure;

forming at least a second contact to said conductive portion of said spacer; and

interconnecting said first plurality of conventional transistors and said second plurality of transistors to form said integrated circuit structure.

12. A method of making an integrated circuit structure as claimed in claim 11 further comprising the steps of:

forming a third plurality of conventional LDD transistors, and interconnecting said third plurality of conventional LDD transistors to said first plurality of said conventional transistors to form said integrated circuit structure.

13. A method of making an integrated circuit structure as claimed in claim 12 further comprising the step of interconnecting said third plurality of conventional LDD transistors to said second plurality of transistors to form said integrated circuit structure.

14. A method of making an integrated circuit structure as claimed in claim 11 further comprising the steps of:

forming a third plurality of conventional LDD transistors, and

interconnecting said third plurality of conventional LDD transistors to said second plurality of transistors to form said integrated circuit structure.