Multi-level flash memory using triple well

• US 6,091,101 A
• Filed: 03/30/1998
• Issued: 07/18/2000
• Est. Priority Date: 03/30/1998
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Worldwide Semiconductor Manufacturing Corp.
• Inventors: Wang, Ling-Sung
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US09/050,741
• Time in Patent Office: 841 Days
• Field of Search: 257/315, 257/316, 257/318, 438/257, 438/258, 365/185.01
• US Class Current: 257/315
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

Claims

1. A multi-level flash memory cell formed in a semiconductor substrate, the memory cell comprising:

(a) a deep n-well formed in said semiconductor substrate;

(b) a p-well formed within said deep n-well;

(c) a first insulating layer formed over said p-well;

(d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer;

(e) source and drain regions formed in said p-well and on either side of said three floating gates;

(f) a second insulating layer atop said three floating gates and said drain and source regions; and

(g) a control gate formed atop said second insulating layer.

2. The flash memory of claim 1 wherein two of said three floating gates are polysilicon sidewall spacers formed adjacent to a remaining one of said three floating gates.

3. The flash memory of claim 1 wherein said control gate is formed from polysilicon.

4. The flash memory of claim 1 wherein said three floating gates comprise a center floating gate, a first sidewall floating gate, and a second sidewall floating gate, said first sidewall floating gate adjacent said source region and said second sidewall floating gate adjacent said drain region.

5. The flash memory of claim 4 wherein data is stored in accordance with:

space="preserve" listing-type="tabular">______________________________________ Second Sidewall First Sidewall Center Floating Data Floating Gate Floating Gate Gate ______________________________________ 00 No Charge No Charge No Charge 01 Stored Charge No Charge No Charge 10 Stored Charge Stored Charge No Charge 11 Stored Charge Stored Charge Stored Charge ______________________________________

6. The flash memory of claim 4 wherein:

(1) for programming charge into said second sidewall floating gate;

(i) a first bias voltage being applied to said control gate,

(ii) a second bias voltage being applied to said drain region, and

(iii) said source region, said p-well and said deep n-well being held at ground;

(2) for programming charge into the first sidewall floating gate;

(i) said first bias voltage being applied to said control gate,

(ii) said second bias voltage being applied to the source region, and

(iii) said drain region, said p-well and said deep n-well being held at ground;

(3) for programming charge into the center floating gate;

(i) said first bias voltage being applied to said control gate,

(ii) a third bias voltage being applied to said p-well, and

(iii) said source region, said drain region, and said deep n-well being held at ground; and

(4) for erasing all of said floating gates;

(i) a fourth bias voltage being applied to said control gate,

(ii) said second bias voltage being applied to said p-well and said deep n-well, and

(iii) said drain region and source region are floating.

7. The flash memory of claim 6 wherein said first bias voltage is 9 volts, said second bias voltage is 5 volts, said third bias voltage is -5 volts, and said fourth bias voltage is -10 volts.

8. The flash memory of claim 6 wherein a read operation of the flash memory cell is performed by applying said second bias voltage volts to said control gate, applying a fifth bias voltage to the drain region, and holding the source region, p-well, and deep n-well at ground.

9. The flash memory of claim 7 wherein said first bias voltage is 9 volts, said second bias voltage is 5 volts, said third bias voltage is -5 volts, said fourth bias voltage is -10 volts, and said fifth bias voltage is 1.5 volts.

10. A multi-level flash memory cell formed in a semiconductor substrate, the memory cell comprising:

(a) a deep n-well formed in said semiconductor substrate;

(b) a p-well formed within said deep n-well;

(c) a first insulating layer formed over said p-well;

(d) a central floating gate, a first outside floating gate, and a second outside floating gate, each of said floating gates lying adjacent to and insulated from one another and lying atop said first insulating layer;

(e) source and drain regions formed in said p-well and on either side of said first floating gate and said second floating gate;

(f) a second insulating layer atop said floating gates and said drain and source regions; and

(g) a control gate formed atop said second insulating layer.