Flash memory cell with self-aligned gates and fabrication process

• US 6,091,104 A
• Filed: 03/24/1999
• Issued: 07/18/2000
• Est. Priority Date: 03/24/1999
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans System Inc (Microchip Technology Incorporated)
• Inventors: Chen, Chiou-Feng
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/275,670
• Time in Patent Office: 482 Days
• Field of Search: 257/315, 257/316, 257/326
• US Class Current: 257/326
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

Claims

1. In a memory cell:

a substrate having an active area, an oxide layer formed on the substrate above the active area, a relatively thin floating gate having a side wall with a rounded curvature positioned above the oxide layer, a control gate which is substantially thicker than the floating gate positioned above and in vertical alignment with the floating gate, a dielectric film between the floating gate and the control gate, a select gate positioned to one side of the control gate and facing the side wall of the floating gate with the rounded curvature, a tunnel oxide between the select gate and the floating gate, and a tunneling path for the migration of electrons during erase operations extending from the side wall of the floating gate with the rounded curvature through the tunnel oxide to the select gate.

2. The memory cell of claim 1 wherein the floating gate has a thickness on the order of 100-1000 Å

, and the control gate has a thickness on the order of 1500-3500 Å

.

3. In a memory cell:

a substrate having an active area, an oxide layer formed on the substrate above the active area, a relatively thin floating gate having a side wall with a rounded curvature positioned above the oxide layer, a dielectric film which is substantially thicker than the floating gate positioned above and in vertical alignment with the floating gate, a select gate positioned to one side of the control gate and facing the side wall of the floating gate with the rounded curvature, a tunnel oxide between the select gate and the floating gate, and a tunneling path for the migration of electrons during erase operations extending from the side wall of the floating gate with the rounded curvature through the tunnel oxide to the select gate.

4. The memory cell of claim 3 wherein the dielectric film comprises a bottom oxide layer which is on the order of 50-300 Å

thick, a nitride layer which is on the order of 1000-2000 Å

thick, and a top oxide layer which is on the order of 200-1000 Å

thick.

5. The memory cell of claim 3 wherein the dielectric film comprises an oxide layer which is on the order of 50-300 Å

thick and a nitride layer which is on the order of 1000-3000Å

thick.

6. In a memory cell:

a substrate having an active area, a relatively thin gate oxide layer formed on the substrate above the active area, a relatively thin floating gate having a side wall with a rounded curvature positioned above the oxide layer, a control gate which is substantially thicker than the floating gate positioned above and in vertical alignment with the floating gate, a dielectric film between the floating gate and the control gate, a select gate positioned to one side of the control gate and facing the side wall of the floating gate with the rounded curvature, a relatively thick oxide layer between the select gate and the floating gate, a source region formed in the substrate with a portion of the source region overlapping beneath the floating gate, and a tunneling path for the migration of electrons during erase operations extending from the floating gate through the gate oxide layer to the overlapping portion of the source region.

7. The memory cell of claim 6 wherein the gate oxide layer has a thickness on the order of 70-120 Å

, and the oxide layer between the select gate and the floating gate has a thickness on the order of 200-1000 Å

.