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Flash memory cell with self-aligned gates and fabrication process

  • US 6,091,104 A
  • Filed: 03/24/1999
  • Issued: 07/18/2000
  • Est. Priority Date: 03/24/1999
  • Status: Expired due to Term
First Claim
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1. In a memory cell:

  • a substrate having an active area, an oxide layer formed on the substrate above the active area, a relatively thin floating gate having a side wall with a rounded curvature positioned above the oxide layer, a control gate which is substantially thicker than the floating gate positioned above and in vertical alignment with the floating gate, a dielectric film between the floating gate and the control gate, a select gate positioned to one side of the control gate and facing the side wall of the floating gate with the rounded curvature, a tunnel oxide between the select gate and the floating gate, and a tunneling path for the migration of electrons during erase operations extending from the side wall of the floating gate with the rounded curvature through the tunnel oxide to the select gate.

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