Dissolvable dielectric method and structure

• US 6,091,149 A
• Filed: 02/18/1999
• Issued: 07/18/2000
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Brennan, William S., Fulford, H. Jim Jr., Bandyopadhyay, Basab, Hause, Fred N.
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US09/251,059
• Time in Patent Office: 516 Days
• Field of Search: 257/751, 257/754, 257/758, 257/760, 257/775, 257/762, 257/763
• US Class Current: 257/758
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

Claims

1. A multilevel interconnect structure comprising:

a semiconductor substrate;

a barrier layer arranged on said semiconductor substrate;

a spaced set of first interconnect conductors arranged in a first plane upon said barrier layer, said first interconnect conductors separated from one another by a first intralevel dielectric comprised of air;

a plurality of vertically oriented interconnect pillars extending upward from said first interconnect conductors, said interconnect pillars comprising a conductive material;

a spaced set of second interconnect conductors arranged upon a second plane vertically displaced above and substantially parallel to said first plane, said second interconnect conductors supported in said second plane by upper ends of said plurality of interconnect pillars whereby an interlevel dielectric between said first interconnect conductors and said second interconnect conductors comprises air; and

a plurality of vertically oriented support pillars extending upward from said barrier layer to a lower surface of said second interconnect conductors.

2. The interconnect structure of claim 1 wherein said barrier layer comprises silicon nitride.

3. The interconnect structure of claim 1 wherein said barrier layer comprises metal oxide.

4. The interconnect structure of claim 1 wherein said barrier layer comprises undoped polysilicon.

5. The interconnect structure of claim 1 wherein said first and second interconnect conductors comprise aluminum, tungsten, or copper.

6. The interconnect structure of claim 1 further comprising a passivation layer formed on an upper surface of said second interconnect conductor layer.