Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM

• US 6,091,263 A
• Filed: 12/12/1997
• Issued: 07/18/2000
• Est. Priority Date: 12/12/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wittig, Ralph, New, Bernard J., Mohan, Sundararajarao, Johnson, Robert Anders
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US08/989,746
• Time in Patent Office: 949 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41, 326/47
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Claims

1. A field programmable gate array (FPGA) comprising:

a first array of configurable logic blocks having a corresponding first set of configuration memory cells;

a first configuration cache memory array coupled to the first array of configurable logic blocks, wherein the first configuration cache memory array stores values to be loaded into the first set of configuration memory cells, thereby reconfiguring the first array of configurable logic blocks;

a second array of configurable logic blocks having a corresponding second set of configuration memory cells;

a second configuration cache memory array coupled to the second array of configurable logic blocks, wherein the second configuration cache memory array stores values to be loaded into the second set of configuration memory cells, thereby reconfiguring the second array of configurable logic blocks; and

a control circuit for transferring values between the first configuration cache memory array and the first set of configuration memory cells, and for independently transferring values between the second configuration cache memory array and the second set of configuration memory cells.

2. The FPGA of claim 1, wherein the first configuration cache memory array stores values for reconfiguring the first array of configurable logic blocks in a plurality of configurations.

3. The FPGA of claim 2, wherein the second configuration cache memory array stores values for reconfiguring the second array of configurable logic blocks in a plurality of configurations.

4. The FPGA of claim 1, wherein the values stored in the first configuration cache memory array comprise a first set of configuration data values for programming corresponding configuration memory cells in the first array of configurable logic blocks in a first configuration, and a first set of state data values for programming corresponding state storage structures in the first array of configurable logic blocks to perform a first function.

5. The FPGA of claim 4, wherein the values stored in the first configuration cache memory array further comprise a second set of configuration data values for programming corresponding configuration memory cells in the first array of configurable logic blocks in a second configuration, and a second set of state data values for programming corresponding state storage structures in the first array of configurable logic blocks to perform a second function.

6. The FPGA of claim 5, further comprising means for loading the first set of configuration data values and the first set of state data values from the first configuration cache memory array to the first set of configuration memory cells, thereby configuring the first array of configurable logic blocks in a first configuration.

7. The FPGA of claim 6, further comprising means for loading the second set of configuration data values and the second set of state data values from the first configuration cache memory array to the first set of configuration memory cells, thereby configuring the first array of configurable logic blocks in a second configuration.

8. The FPGA of claim 6, further comprising means for loading the first set of configuration data values and the second set of state data values from the first configuration cache memory array to the first set of configuration memory cells, thereby configuring the first array of configurable logic blocks in a second configuration.

9. The FPGA of claim 1, wherein each of the configurable logic blocks in the first array of configurable logic blocks has a corresponding local configuration memory block in the first configuration cache memory array.

10. The FPGA of claim 9, wherein each local configuration memory block stores values associated with a plurality of configurations of a corresponding configurable logic block.

11. The FPGA of claim 1, further comprising a configuration port for accessing the first and second configuration cache memory arrays.

12. The FPGA of claim 1, wherein the control circuit is configured to load values from the first configuration cache memory array to the first set of configuration memory cells over a plurality of operating cycles.

13. The FPGA of claim 12, wherein the control circuit is configured to load values from the second configuration cache memory array to the second set of configuration memory cells over a plurality of operating cycles.

14. The FPGA of claim 1, wherein the first array of configurable logic blocks is arranged in a plurality of rows and the first configuration cache memory array is arranged in a plurality of rows, wherein the rows of the first array of configurable logic blocks are interleaved with the rows of the first configuration cache memory array.

15. The FPGA of claim 14, wherein the second array of configurable logic blocks is arranged in a plurality of rows and the second configuration cache memory array is arranged in a plurality of rows, wherein the rows of the second array of configurable logic blocks are interleaved with the rows of the second configuration cache memory array.

16. The FPGA of claim 15, wherein the first array of configurable logic blocks and the first configuration cache memory array are located on a first half of the FPGA, and the second array of configurable logic blocks and the second configuration cache memory array are located on a second half of the FPGA.

17. The FPGA of claim 1, wherein the values stored in the first configuration cache memory array comprise a first set of state data values for programming corresponding flip-flops in the configurable logic block.

18. The FPGA of claim 1, wherein the values stored in the first configuration cache memory array comprise a first set of state data values for programming corresponding function generators in the first array of configurable logic blocks to perform a first function.

19. A field programmable gate array (FPGA) comprising:

a first array of configurable logic blocks having a corresponding first set of configuration memory cells;

a first configuration cache memory array coupled to the first array of configurable logic blocks, wherein the first configuration cache memory array stores values to be loaded into the first set of configuration memory cells, thereby reconfiguring the first array of configurable logic blocks;

a second array of configurable logic blocks having a corresponding second set of configuration memory cells;

a second configuration cache memory array coupled to the first configuration cache memory array, wherein the second configuration cache memory array stores values to be loaded into the first set of configuration memory cells, thereby reconfiguring the first array of configurable logic blocks; and

control circuitry for transferring values from the second configuration cache memory array to the first configuration cache memory array.

20. A field programmable gate array (FPGA) comprising:

a first array of configurable logic blocks having a corresponding first set of configuration memory cells;

a first configuration cache memory array coupled to the first array of configurable logic blocks, wherein the first configuration cache memory array stores values to be loaded into the first set of configuration memory cells, thereby reconfiguring the first array of configurable logic blocks;

a second array of configurable logic blocks having a corresponding second set of configuration memory cells;

a second configuration cache memory array coupled to the second array of configurable logic blocks; and

a control circuit for configuring the second configuration cache memory array to either store values to be loaded into the second set of configuration memory cells, thereby reconfiguring the second array of configurable logic blocks, or to operate as a random access memory.

21. A method of operating a field programmable gate array (FPGA) comprising the steps of:

providing a first array of configurable logic blocks and a second array of configurable logic blocks on the FPGA;

providing a first configuration cache memory array coupled to the first array of configurable logic blocks and a second configuration cache memory array coupled to the second array of configurable logic blocks;

reconfiguring the first array of configurable logic blocks in response to values stored in the first configuration cache memory array; and

reconfiguring the second array of configurable logic blocks in response to values stored in the second configuration cache memory array, wherein the step of reconfiguring the first array of configurable logic blocks is performed independent of the step of reconfiguring the second array of configurable logic blocks, thereby enabling partial reconfiguration of the FPGA.

22. The method of claim 21, wherein the step of reconfiguring the first array of configurable logic blocks further comprises the step of loading the values stored in the first configuration memory array to the first array of configurable logic blocks over a plurality of operating cycles.

23. The method of claim 22, wherein the values stored in the first configuration memory array comprise a first set of configuration data values for programming corresponding configuration memory cells in the first array of configurable logic blocks in a first configuration, and a first set of state data values for programming corresponding state storage structures in the first array of configurable logic blocks to perform a first function, the method further comprising the steps of:

clearing the first array of configurable logic blocks;

loading the first set of configuration data values into the first array of configurable logic blocks over a plurality of operating cycles; and

loading the first set of state data values into the first array of configurable logic blocks.

24. The method of claim 22, wherein the values stored in the first configuration memory array comprise a first set of configuration data values for programming corresponding configuration memory cells in the first array of configurable logic blocks in a first configuration, and wherein the first array of configurable logic blocks includes a plurality of state storage structures which store a first set of state data values, the method further comprising the steps of:

storing the first set of state data values in the first configuration memory array;

clearing the first array of configurable logic blocks;

loading the first set of configuration data values from the first configuration memory array to the first array of configurable logic blocks over a plurality of operating cycles; and

loading the first set of state data values from the first configuration memory array into the first array of configurable logic blocks.

25. A method of operating a field programmable gate array (FPGA) comprising the steps of:

providing a first array of configurable logic blocks and a second array of configurable logic blocks on the FPGA;

providing a first configuration cache memory array coupled to the first array of configurable logic blocks and a second configuration cache memory array coupled to the first configuration cache memory array;

reconfiguring the first array of configurable logic blocks in response to values stored in the first configuration cache memory array;

transferring the values stored in the second configuration cache memory array to the first configuration cache memory array; and

reconfiguring the first array of configurable logic blocks in response to values transferred from the second configuration cache memory array to the first configuration cache memory array.

26. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks;

an array of random access memory (RAM) blocks for storing one or more sets of configuration data values for configuring the configurable logic blocks, wherein each RAM block has a corresponding configurable logic block;

a plurality of configuration buses, wherein each configuration bus couples a RAM block to a corresponding configurable logic block; and

a control circuit for transferring values between the array of configurable logic blocks and the array of RAM blocks, wherein the control circuit is configured to route a set of configuration data values from the RAM blocks to the configurable logic blocks on the configuration buses over a plurality of cycles.

27. The FPGA of claim 26, wherein each RAM block comprises:

a configuration data cache memory for storing configuration data values for configuring a configurable logic block; and

a state data cache memory for storing state data values associated with the configurable logic block.

28. The FPGA of claim 27, wherein each RAM block further comprises a memory dedicated to storing state data values.

29. The FPGA of claim 26, wherein each RAM block further comprises a plurality of local cache memories, wherein each local cache memory comprises a configuration data cache memory for storing configuration data values for configuring a configurable logic block, and a state data cache memory for storing state data values associated with the configurable logic block.

30. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks;

an array of random access memory (RAM) blocks for storing one or more sets of configuration data values for configuring the configurable logic blocks, wherein each RAM block has a corresponding configurable logic block; and

a plurality of configuration buses, wherein each configuration bus couples a RAM block to a corresponding configurable logic block, wherein the configuration data values are routed from the RAM blocks to the configurable logic blocks on the configuration buses over a plurality of cycles, wherein the configuration buses are bi-directional, such that the configuration data values are also routed from the configurable logic blocks to the RAM blocks on the configuration buses.

31. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks;

an array of random access memory (RAM) blocks for storing one or more sets of configuration data values for configuring the configurable logic blocks, wherein each RAM block has a corresponding configurable logic block;

a plurality of configuration buses, wherein each configuration bus couples a RAM block to a corresponding configurable logic block, wherein the configuration data values are routed from the RAM blocks to the configurable logic blocks on the configuration buses over a plurality of cycles;

a plurality of random access buses, wherein each random access bus couples a RAM block to a corresponding configurable logic block, each of the random access buses comprising an address bus for providing an address from the configurable logic block to the RAM block, a first data bus for providing data from the configurable logic block to the RAM block, and a second data bus for providing data from the RAM block to the configurable logic block; and

circuitry for accessing the RAM blocks as random access memory through the configurable logic blocks using the random access buses.

32. The FPGA of claim 31, further comprising an expansion bus which is programmable to couple adjacent RAM blocks.

33. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks;

an array of random access memory (RAM) blocks for storing one or more sets of configuration data values for configuring the configurable logic blocks, wherein each RAM block has a corresponding configurable logic block, and wherein each RAM block comprises;

a configuration data cache memory for storing configuration data values for configuring a configurable logic block; and

a state data cache memory for storing state data values associated with the configurable logic block;

a plurality of configuration buses, wherein each configuration bus couples a RAM block to a corresponding configurable logic block, wherein the configuration data values are routed from the RAM blocks to the configurable logic blocks on the configuration buses over a plurality of cycles; and

means for independently transferring state data values between the state data cache memory and the configurable logic block.

34. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks;

an array of random access memory (RAM) blocks; and

a plurality of random access buses, wherein each random access bus is programmable to couple a RAM block to a corresponding configurable logic block, each of the random access buses comprising an address bus for providing an address from the configurable logic block to the RAM block, a first data bus for providing data from the configurable logic block to the RAM block, and a second data bus for providing data from the RAM block to the configurable logic block; and

circuitry for accessing the RAM blocks as random access memory through the configurable logic blocks using the first buses.

35. The FPGA of claim 34, further comprising an expansion bus which is programmable to couple adjacent RAM blocks.

36. The FPGA of claim 35, wherein the expansion bus comprises a first expansion bus which selectively couples adjacent RAM blocks along a first direction, and a second expansion bus which selectively couples adjacent RAM blocks along a second direction.

37. The FPGA of claim 34, further comprising a communications port providing an interface between the RAM blocks and circuitry external to the FPGA.