Frequency band select phase lock loop device

• US 6,091,304 A
• Filed: 09/22/1998
• Issued: 07/18/2000
• Est. Priority Date: 09/22/1998
• Status: Expired due to Term

• Current Assignee: LG Information & Communications Ltd. (LG Corporation)
• Original Assignee: LG Information & Communications Ltd. (LG Corporation)
• Inventors: Harrer, James Richard
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/158,289
• Time in Patent Office: 665 Days
• Field of Search: 331/10, 331/11, 331/16, 331/17, 331/36 C, 331/117 R, 331/117 FE, 331/177 V, 331/167
• US Class Current: 331/10
• CPC Class Codes: H03J 5/244 using electronic means
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A multi-band phase lock loop (PLL) device for use in a communication system. The PLL comprises a frequency reference oscillator, a reference frequency divider, a phase and frequency detector, a filter and compensation circuit, a microcontroller, a multi-band voltage controlled oscillator (VCO), and a feedback divider. A fast feedback signal is provided to the VCO for phase locking operation. A slow feedback signal is used by the microcontroller to generate a frequency adjust signal for frequency band centering for the VCO. The microcontroller also controls the VCO to change the frequency band of operation. The PLL device may be used in a communication system that operate in both the cellular frequency band and the PCS frequency band.

Claims

1. A phase lock loop (PLL) device, comprising:

a phase and frequency detector coupled to a frequency reference signal having a first frequency and to a second input frequency signal for generating an output error signal based on frequency and phase information contained in the frequency reference signal and the second input frequency signal;

a filter and compensation circuit coupled to the output error signal of the phase and frequency detector, the filter and compensation circuit including a first low-pass filter for generating a first feedback signal, and a second low-pass filter for generating a second feedback signal based on the error signal;

a controller coupled to the second feedback signal for generating a frequency adjust signal; and

a voltage controlled oscillator (VCO) coupled to the first feedback signal and to the frequency adjust signal for generating an output frequency signal to be provided to the phase and frequency detector as its second input frequency signal, the output frequency signal having a second frequency which is controlled by both the first feedback signal and the frequency adjust signal;

whereby the phase and frequency detector, the filter and compensation circuit and the voltage controlled oscillator form a phase lock loop to lock the second frequency to the first frequency.

2. The PLL device of claim 1, wherein the VCO comprises a first and a second varactor, the first varactor being controlled by the first feedback signal and the second varactor being controlled by the frequency adjust signal, and wherein the second frequency depends on the capacitance of both the first and the second varactor.

3. The PLL device of claim 2, wherein the first and second varactors are connected in parallel.

4. The PLL device of claim 2, wherein the second feedback signal is slower-varying than the first feedback signal.

5. The PLL device of claim 1, wherein the controller generates the frequency adjust signal based on the second feedback signal so that the second feedback signal falls within a predetermined voltage range.

6. The PLL device of claim 5, wherein the frequency adjust signal is a DC voltage, and wherein the controller changes the DC voltage in a first direction if it determines that the second feedback signal is higher than a predetermined upper limit value, changes the DC voltage in a second direction if it determines that the second feedback signal is lower than a predetermined lower limit value, and otherwise leaves the DC voltage unchanged.

7. The PLL device of claim 6, wherein the processor repeats the determining and changing steps, and delays for a predetermined period of time after a changing step before the next determining step.

8. The PLL device of claim 7, wherein the period of delay is zero.

9. The PLL device of claim 5, wherein the VCO comprises a first varactor coupled to the first feedback signal and a second varactor coupled to the frequency adjust signal.

10. The PLL device of claim 1, wherein the filter and compensation circuit further comprises a buffer for preventing interaction between the first and second feedback signals.

11. A phase lock loop (PLL) device, comprising:

a phase and frequency detector coupled to a frequency reference signal having a first frequency and to a second input frequency signal for generating an output error signal based on frequency and phase information contained in the frequency reference signal and the second input frequency signal;

a filter and compensation circuit coupled to the output error signal of the phase and frequency detector for generating a first and a second feedback signal based on the error signal;

a controller coupled to the second feedback signal and to a band select input for generating a frequency adjust signal and a band select signal; and

a voltage controlled oscillator (VCO) coupled to the first feedback signal, the band select signal, and the frequency adjust signal for generating an output frequency signal having a second frequency to be provided to the phase and frequency detector as its second input frequency signal, the VCO comprising at least one first varactor controlled by the feedback signal, a first inductor connected in parallel with the first varactor, at least one second inductor selectively connected to the first varactor and the first inductor by the band select signal, and at least one second varactor controlled by the frequency adjust signal and selectively connected to the first varactor and the first inductor by the band select signal;

whereby the phase and frequency detector, the filter and compensation circuit and the VCO form a phase lock loop to lock the second frequency to the first frequency.

12. The PLL device of claim 11, wherein the second frequency falls within one of a plurality of frequency bands dependent upon the connection of the second inductor controlled by the band select signal, and wherein the value of the second frequency within a frequency band is controlled by the first feedback signal and the frequency adjust signal.

13. The PLL device of claim 11, wherein the controller generates the frequency adjust signal based on the second feedback signal so that the second feedback signal falls within a predetermined voltage range.

14. A method of generating a phase locked frequency signal, comprising:

providing a voltage controlled frequency signal having a second frequency using a voltage controlled oscillator (VCO), the VCO comprising at least one first varactor and at least one second varactor connected to the first varactor, the second frequency being dependant on both the first and second varactors;

detecting the frequency and phase information contained in the voltage controlled frequency signal and a frequency reference signal having a first frequency to generate an output error signal based on the detected information;

passing the error signal through a filter and compensation circuit comprising a first low-pass filter to provide a first feedback signal and a second low pass filter to provide a second feedback signal;

controlling the first varactor in the VCO using the first feedback signal to vary the second frequency;

generating a frequency adjust signal based on the second feedback signal; and

controlling the capacitance of the second varactor using the frequency adjust signal.

15. The method of claim 14, wherein the first and second varactors are connected in parallel.

16. The method of claim 14, wherein the second feedback signal is slower-varying than the first feedback signal.

17. The method of claim 14, wherein the frequency adjust signal is generated by comparing the second feedback signal to predetermined upper and lower limit values.

18. The method of claim 17, wherein the frequency adjust signal is a DC voltage, and wherein when generating the frequency adjust signal, the DC voltage is changed in a first direction if the second feedback signal is higher than the upper limit value, changed in a second direction if the second feedback signal is lower than the lower limit value, and otherwise unchanged.

19. The method of claim 18, wherein the changing step is repeated after a delay or a predetermined time period.

20. The method of claim 19, wherein the period of delay is zero.

21. The method of claim 14, wherein the filter and compensation circuit prevents interaction between the first and second feedback signals.

22. A method of generating a band-selectable phase locked frequency signal, comprising:

providing a voltage controlled frequency signal having a second frequency using a voltage controlled oscillator (VCO), the VCO comprising at least one first varactor and a first inductor connected in parallel;

detecting the frequency and phase information contained in the voltage controlled frequency signal and a frequency reference signal having a first frequency to generate an output error signal based on the detected information;

processing the error signal to provide a first and a second feedback signal;

controlling the first varactor in the VCO using the first feedback signal to vary the second frequency;

providing a band select signal;

selectively connecting or disconnecting at least one second inductor to the first varactor and the first inductor in the VCO based on the band select signal to change the second frequency;

generating a frequency adjust signal based on the second feedback signal; and

selectively connecting or disconnecting at least one second varactor to the first varactor and the first inductor in the VCO based on the band select signal; and

controlling the capacitance of the second varactor connected to the first varactor and the first inductor using the frequency adjust signal.

23. The method of claim 22, wherein the second frequency falls within one of a plurality of frequency bands dependent upon the connection of the second inductor controlled by the band select signal, and wherein the value of the second frequency within a frequency band is a controlled by the first feedback signal and the frequency adjust signal.

24. The method of claim 22, wherein the frequency adjust signal is generated based on the second feedback signal so that the second feedback signal falls within a predetermined voltage range.