Method and apparatus for wireless RS232 communication

• US 6,091,764 A
• Filed: 10/29/1997
• Issued: 07/18/2000
• Est. Priority Date: 10/29/1997
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Silk, S. David, Porrett, Edward C.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Liu, Shuwang
• Application Number:
  US08/959,768
• Time in Patent Office: 993 Days
• Field of Search: 375/219, 375/232, 375/346, 375/347, 375/130, 375/222, 370/535, 370/451, 370/349, 395/200.62
• US Class Current: 375/219
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A controller circuit (107) between a transceiver (104) and an RS232communication port (103) provides wireless communication to a remote unit and includes a transmitting and receiving mode indicator (503), a first delay circuit (506) for delaying a packet of data (501) before being transmitted, a timer (502) counting a period of time during which delaying termination of transmitting mode following a last data bit of the packet of data (501). Further, a receive signal detector (504) produces a carrier detect signal (521) and its delayed version (525) through a second delay (522) when a data packet (520) is received from the transceiver (104), first and second AND gates (523, 528) and a third delay circuit (526) receive signals (525and 520) to produce a reformatted received data packet (529) compatible to the RS232format for input to the RS232communication port (103).

Claims

1. A controller circuit between a transceiver and an RS232 communication port, comprising:

an indicator indicating transmit mode when receiving from said communication port an RS232 compatible packet of data to be transmitted which places said transceiver in transmitting mode, and indicating at other times receive mode which places said transceiver in receiving mode;

a first delay circuit for delaying said packet of data for a period of time before being inputted to said transceiver for subsequent transmission;

a timer counting a period of time following transmission of a last data bit from said packet of data for delaying termination of said transceiver transmitting mode beyond said last data bit of said packet of data;

a receive signal detector producing a carrier detect signal when a second baseband demodulated data packet is received from said transceiver while said indicator is indicating receiving mode;

a second delay circuit receiving said carrier detect signal producing a delayed said carrier detect signal;

a first AND gate receiving said delayed carrier detect signal and said received data packet producing a first delayed received data packet;

a third delay circuit receiving said first delayed received data packet producing a second delayed received data packet; and

a second AND gate receiving said carrier detect signal and said second delayed received data packet producing a reformatted received data packet compatible to RS232 format for being inputted to said RS232 communication port.

2. The controller circuit as recited in claim 1 wherein said transceiver is an infrared transceiver.

3. The controller circuit as recited in claim 1 wherein said first delay circuit delaying said packet of data for said period of time equal to a period of two data bits, and said transceiver is transmitting data bits having zero logic value during said period of two data bits.

4. The controller circuit as recited in claim 1 wherein said timer counting said period of time equal to a period of ten data bits, and said transceiver is transmitting data bits having zero logic value during said period of ten data bits.

5. A controller circuit between a receiver and a communication port, comprising:

a receive signal detector producing a carrier detect signal when a baseband demodulated data packet is received from said receiver;

a first delay circuit receiving said carrier detect signal producing a delayed said carrier detect signal;

a first AND gate receiving said delayed carrier detect signal and said received data packet producing a first delayed received data packet;

a second delay circuit receiving said first delayed received data packet producing a second delayed received data packet; and

a second AND gate receiving said carrier detect signal and said second delayed received data packet producing a reformatted received data packet inputted to said communication port.