×

Frequency synthesis architecture in a satellite receiver

  • US 6,091,931 A
  • Filed: 06/18/1997
  • Issued: 07/18/2000
  • Est. Priority Date: 06/18/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A DBS receiver front end comprising:

  • a tuner chip which includes;

    a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency;

    a downconverter coupled to the tuning oscillator to receive a tuning frequency signal, wherein the downconverter is further coupled to receive a receive signal, wherein the downconverter is configured to responsively provide a product signal, wherein the tuner chip is configured to convert the product signal into a baseband signal; and

    a demodulator/decoder chip which includes;

    a programmable counter coupled to count cycles of the tuning frequency signal, wherein the programmable counter is configured to responsively provide a frequency-divided signal to a phase detector, wherein the phase detector is configured to compare the frequency-divided signal with a reference frequency, and wherein the phase detector is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency signal to have a frequency which is a multiple of the reference frequency; and

    a decoder operably coupled to receive said baseband signal and configured to convert the baseband signal to a decoded signal.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×