Frequency synthesis architecture in a satellite receiver
First Claim
1. A DBS receiver front end comprising:
- a tuner chip which includes;
a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency;
a downconverter coupled to the tuning oscillator to receive a tuning frequency signal, wherein the downconverter is further coupled to receive a receive signal, wherein the downconverter is configured to responsively provide a product signal, wherein the tuner chip is configured to convert the product signal into a baseband signal; and
a demodulator/decoder chip which includes;
a programmable counter coupled to count cycles of the tuning frequency signal, wherein the programmable counter is configured to responsively provide a frequency-divided signal to a phase detector, wherein the phase detector is configured to compare the frequency-divided signal with a reference frequency, and wherein the phase detector is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency signal to have a frequency which is a multiple of the reference frequency; and
a decoder operably coupled to receive said baseband signal and configured to convert the baseband signal to a decoded signal.
7 Assignments
0 Petitions
Accused Products
Abstract
An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency to have a frequency which is a multiple of the resonance frequency. The demodulator/decoder chip also has a decoder which receives the baseband signal and converts it to a decoded signal.
-
Citations
15 Claims
-
1. A DBS receiver front end comprising:
-
a tuner chip which includes; a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency; a downconverter coupled to the tuning oscillator to receive a tuning frequency signal, wherein the downconverter is further coupled to receive a receive signal, wherein the downconverter is configured to responsively provide a product signal, wherein the tuner chip is configured to convert the product signal into a baseband signal; and a demodulator/decoder chip which includes; a programmable counter coupled to count cycles of the tuning frequency signal, wherein the programmable counter is configured to responsively provide a frequency-divided signal to a phase detector, wherein the phase detector is configured to compare the frequency-divided signal with a reference frequency, and wherein the phase detector is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency signal to have a frequency which is a multiple of the reference frequency; and a decoder operably coupled to receive said baseband signal and configured to convert the baseband signal to a decoded signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A tuner chip which comprises:
-
a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency; a downconverter coupled to the tuning oscillator to receive a tuning frequency signal, wherein the downconverter is further coupled to receive a receive signal, wherein the downconverter is configured to responsively provide a product signal, wherein the tuner chip is configured to convert the product signal into a baseband signal; a prescaler coupled to receive the tuning frequency signal from the tuning oscillator, wherein the prescaler is configured to provide a reduced frequency signal to an off-chip programmable counter; a phase detector coupled to the off-chip programmable counter to receive a frequency-divided signal and configured to compare the frequency divided signal to a reference frequency; and a charge pump coupled to the phase detector and configured to responsively provide a correction voltage to a loop filter which determines the resonance frequency of the tank circuit. - View Dependent Claims (10, 11, 12)
-
-
13. A method for synthesizing a tuning frequency in a DBS receiver front end having a tuner chip and a demodulator/decoder chip, wherein the method comprises:
-
coupling a tuning oscillator on the tuner chip to a tank circuit; configuring a prescaler on the tuner chip to produce a reduced frequency signal from a tuning frequency signal provided by the tuning oscillator; programming a counter on the demodulator/decoder chip to count a desired number of reduced frequency signal cycles for each cycle of a frequency divided signal provided by the counter; configuring a phase detector to compare a reference frequency signal with the frequency divided signal to provide a phase difference signal; coupling the phase difference signal to a charge pump on the tuner chip; coupling the charge pump to provide a correction voltage to a loop filter; and coupling the loop filter to control a resonance frequency of the tank circuit. - View Dependent Claims (14, 15)
-
Specification