Memory management method

• US 6,092,160 A
• Filed: 09/26/1997
• Issued: 07/18/2000
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Marsters, Jonathan Iain
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US08/938,533
• Time in Patent Office: 1,026 Days
• Field of Search: 711/156, 711/103, 365/185.11, 455/550
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H04M 1/724 User interfaces specially adapted for cordless or mobile telephones

Abstract

A memory management method, comprising determining a number of used memory locations for a first memory region exceeding a predetermined threshold. Identifying a second memory region available for storing electronic signals, and storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the first memory region. Thereby levelling wear of the memory.

Claims

1. A memory management method, comprising

determining a number of used memory locations for a first memory region exceeding a predetermined threshold,

identifying a second memory region available for storing electronic signals,

storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the first memory region,

determining from a plurality of first memory regions a third memory region having undergone a predetermined number of erases, and

storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the third memory region.

4. A memory management method according to claim 1 wherein said memory regions comprise a flash memory device having regions for storing parametric data and executable code instructions for the operation of the flash memory device, said method further including the steps of:

as a precursor to an erase cycle of the flash memory device, transferring the executable code to a further second memory device other than the flash memory device to provide executable code therein, and

controlling the erase cycle by using the transferred executable code from the second memory device.

2. A memory management method, comprising determining a first memory region having undergone a least number of erases and a second memory region having undergone a greatest number of erases from a plurality of memory regions,

determining a difference between the least number and greatest number exceeding a predetermined criterion,

storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the first memory region and

storing in the first memory region electronic signals corresponding to electronic signals representative of parametric data stored in the second memory region.

3. A method of managing a first flash memory device, the flash memory device having regions for storing parametric data and executable code instructions for at least the operation of the memory device, comprising the steps of:

as a precursor to an erase cycle of the flash memory device, transferring the executable code to a further second memory device other than the first flash memory device to provide executable code therein, and

controlling the erase cycle by using the transferred executable code from the second memory device.

5. Electronic apparatus for memory management by a computer processor comprising:

means for determining a number of used memory locations for a first memory region exceeding a predetermined threshold,

means for identifying a second memory region available for storing electronic signals,

means for storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the first memory region,

means for determining from a plurality of first memory regions a third memory region having undergone a predetermined number of erases, and

means for storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the third memory region.

6. A medium for storing machine-readable instructions further comprising

means for determining a number of used memory locations for a first memory region of said medium which exceed a predetermined threshold,

means for identifying a second memory region of said medium available for storing electronic signals,

means for storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the first memory region,

means for determining from a plurality of first memory regions a third memory region of said medium having undergone a predetermined number of erases, and

means for storing in the second memory region electronic signals corresponding to electronic signals representative of parametric data stored in the third memory region.