Data processor and data processing system having two translation lookaside buffers

• US 6,092,172 A
• Filed: 10/15/1997
• Issued: 07/18/2000
• Est. Priority Date: 10/16/1996
• Status: Expired due to Term

• Current Assignee: Advanced Processor Technologies LLC (Acacia Research Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchiyama, Kunio, Nishii, Osamu, Nishimoto, Junichi, Toda, Makoto, Arakawa, Fumio, Narita, Susumu, Ito, Masayuki
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US08/950,668
• Time in Patent Office: 1,007 Days
• Field of Search: 711/133, 711/166, 711/154, 711/200, 711/205, 711/206, 711/207
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Claims

1. A data processor, comprising:

a central processing unit;

a first translation lookaside buffer in which a part of address translation information for translating a virtual address treated by said central processing unit to a physical address is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to a virtual page number outputted by said central processing unit;

a second translation lookaside buffer in which address translation information regarding an instruction address out of the address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching said second translation lookaside buffer being coupled to said first translation buffer; and

a buffer control circuit which, when associative retrieval with respect to a virtual page number in said second translation lookaside buffer results in a retrieval miss, a virtual page number concerned with the retrieval miss is applied to said first translation lookaside buffer for an associative retrieval therein and the address translation information for said associative retrieval in said first translation lookaside buffer with respect to said virtual page number concerned with the retrieval miss is supplied to said second translation lookaside buffer.

2. A data processor according to claim 1, wherein when the result of the associative retrieval with respect to a virtual page number in said second translation lookaside buffer results in the retrieval miss and the virtual page number concerned with the retrieval miss is applied to said first translation lookaside buffer for associative retrieval resulting in a retrieval miss, said central processing unit writes the address translation information including a virtual page number regarding said retrieval miss into said first translation lookaside buffer by an exceptional process.

3. A data processor according to claim 1, further comprising a data cache memory in which a cache entry of data is stored in correspondence to the physical page number and to which the physical page number that was associatively retrieved by said first translation lookaside buffer is supplied and which associatively retrieves a cache entry corresponding to said physical page number.

4. A data processor according to claim 3, wherein a part of said data cache memory is mapped into a predetermined area which is specified by the virtual address, and said data processor further comprises a first RAM area discrimination control circuit for detecting an access to said predetermined area and for allowing said data cache memory to perform a random accessing operation.

5. A data processor according to claim 4, further comprising:

a first index mode designating circuit,

wherein said first index mode designating circuit switches a specified bit of said virtual address and an upper bit than said specified bit and supplies the switched bit to said data cache memory.

6. A data processor according to claim 3, wherein the translation information which is stored in said first translation lookaside buffer has protection information to specify an access right to a page and said data processor further comprises an access protecting circuit for discrimination the access right to said page on the basis of the protection information of the translation information regarding an associated-hit.

7. A data processor according to claim 6, further comprising a detecting circuit to which the physical page number outputted by said associated-hit due to the association retrieval by said first translation lookaside buffer is inputted and which discriminates whether said inputted physical page number coincides with a physical page allocated to an I/O register space in said data processor, suppresses the associative retrieving operation of said data cache memory by a coincidence detection, and allows an I/O register to be directly accessed.

8. A data processor according to claim 3, wherein the translation information which is stored in said first translation lookaside buffer has cache write mode specified information to specify which one of a write-through and a write-back is used as a write control mode for said data cache memory and said processor further comprises a cache write control circuit for controlling the mode of a cache write to said page on the basis of said cache write mode information included in the translation information regarding an associated-hit.

9. A data processor according to claim 1, further comprising an instruction cache memory in which a cache entry of an instruction is stored in correspondence to the physical page number and to which the physical page number that was associatively retrieved by said second translation lookaside buffer is supplied and which associatively retrieves a cache entry corresponding to said physical page number.

10. A data processor according to claim 9, wherein a part of said instruction cache memory is mapped into a predetermined area that is specified by the virtual address and said data processor further comprises a second RAM area discrimination control circuit for detecting an access to said predetermined area and for allowing said instruction cache memory to perform a ransom accessing operation.

11. A data processor according to claim 10, further comprising:

a second index mode designating circuit,

wherein said second index mode designating circuit switches a specified bit of said virtual address and an upper bit than said specified bit and supplies the switched bit to said instruction cache memory.

12. A data processing system, comprising:

a data processor; and

an external memory connected to said data processor,

wherein said data processor comprises;

central processing unit

a first translation lookaside buffer in which a part of address translation information for translating a virtual address treated by said central processing unit to a physical address has been stored and which associatively retrieves a physical page number corresponding to said virtual page number that is outputted by said central processing unit from said address translation information; and

a second translation lookaside buffer in which address translation information regarding an instruction address out of the address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching, said second translation lookaside buffer being coupled to said first translation lookaside buffer so that when associative retrieval with respect to a virtual page number in said second buffer results in a retrieval miss, a virtual page number concerned with said retrieval miss is applied to said first translation lookaside buffer for an associative retrieval therein and address translation information for said associative retrieval in said first translation lookaside buffer with respect to said virtual page number concerned with said retrieval miss is supplied to said second translation lookaside buffer stored into said first or second translation lookaside buffer by a control of an OS of said data processor.

13. A data processing system according to claim 12, wherein said external memory stores the address translation information to translate said virtual address to said physical address, and a part of the information used recently in said address translation information is stored into said first or second translation lookaside buffer by a control of an OS of said data processor.

14. A data processing system according to claim 12, wherein when a retrieval result of said data cache memory indicates a read miss, information as much as one cache line including data regarding the miss is read out from said external memory and is stored into said data cache memory.

15. A data processing system according to claim 12, wherein when a retrieval result of said instruction cache memory indicates a read miss, information as much as one cache line including an instruction regarding the miss is read out from said external memory and is stored into said instruction cache memory.

16. A data processor, comprising:

a central processing unit;

a first translation lookaside buffer in which a part of address translation information to translate a virtual address that is treated by said central processing unit into a physical address is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to a virtual page number that is outputted by said central processing unit;

a second translation lookaside buffer in which address translation information regarding an instruction address in address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching;

a buffer control circuit for, when a result of the associative retrieval by said second translation lookaside buffer indicates a retrieval miss, associatively retrieving said first translation lookaside buffer by a virtual page number according to said retrieval miss, and for supplying the address translation information retrieved by said association retrieval to said second translation lookaside buffer;

a data cache memory in which a cache entry of data is stored in correspondence to the physical page number and to which the physical page number that was associatively retrieved by said first translation lookaside buffer is supplied and which associatively retrieves a cache entry corresponding to said physical page number,

wherein the translation information which is stored in said first translation lookaside buffer has protection information to specify an access right to a page and said data processor further comprises an access protecting circuit for discrimination the access right to said page on the basis of the protection information of the translation information regarding an associated-hit; and

a detecting circuit to which the physical page number that is outputted by said associated-hit due to the association retrieval by said first translation lookaside buffer is inputted and which discriminates whether said inputted physical page number coincides with a physical page allocated to an I/O register space in said data processor, suppresses the associative retrieving operation of said data cache memory by a coincidence detection, and allows an I/O register to be directly accessed.

17. A data processor, comprising:

a central processing unit;

a first translation lookaside buffer in which a part of address translation information to translate a virtual address that is treated by said central processing unit into a physical address is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to a virtual page number that is outputted by said central processing unit;

a second translation lookaside buffer in which address translation information regarding an instruction address in address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching;

a buffer control circuit for, when a result of the associative retrieval by said second translation lookaside buffer indicates a retrieval miss, associatively retrieving said first translation lookaside buffer by a virtual page number according to said retrieval miss, and for supplying the address translation information retrieved by said association retrieval to said second translation lookaside buffer;

a data cache memory in which a cache entry of data is stored in correspondence to the physical page number and to which the physical page number that was associatively retrieved by said first translation lookaside buffer is supplied and which associatively retrieves a cache entry corresponding to said physical page number,

wherein a part of said data cache memory is mapped into a predetermined area which is specified by the virtual address;

a first RAM area discrimination control circuit for detecting an access to said predetermined area and for allowing said data cache memory to perform a random accessing operation; and

a first index mode designating circuit,

wherein said first index mode designating circuit switches a specified bit of said virtual address and an upper bit than said specified bit and supplies the switched bit to said data cache memory.

18. A data processor, comprising:

a central processing unit;

a first translation lookaside buffer in which a part of address translation information to translate a virtual address that is treated by said central processing unit into a physical address is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to a virtual page number that is outputted by said central processing unit;

a second translation lookaside buffer in which address translation information regarding an instruction address in address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching;

a buffer control circuit for, when a result of the associative retrieval by said second translation lookaside buffer indicates a retrieval miss, associatively retrieving said first translation lookaside buffer by a virtual page number according to said retrieval miss, and for supplying the address translation information retrieved by said association retrieval to said second translation lookaside buffer;

an instruction cache memory in which a cache entry of an instruction is stored in correspondence to the physical page number and to which the physical page number that was associatively retrieved by said second translation lookaside buffer is supplied and which associatively retrieves a cache entry corresponding to said physical page number,

wherein a part of said instruction cache memory is mapped into a predetermined area that is specified by the virtual address;

a second RAM area discrimination control circuit for detecting an access to said predetermined area and for allowing said instruction cache memory to perform a ransom accessing operation; and

a second index mode designating circuit,

wherein said second index mode designating circuit switches a specified bit of said virtual address and an upper bit than said specified bit and supplies the switched bit to said instruction cache memory.