Dynamically reconfigurable distributed integrated circuit processor and method
First Claim
1. A dynamically reconfigurable distributed integrated circuit processor comprising:
- at least one two-layer integrated circuit matrix with a first layer and a second layer;
the first layer having a plurality of operative microcomputer modules of computers distributed in one or more computational clusters and linked together by a network of local communications connecting buses;
the second layer being a network of global communications connecting buses that are coherent with the first layer through at least one pathway batch controller proximate at least one network node of the global communications connecting buses;
each of the operative microcomputer modules having at least three n-bit active operand inputs, one instruction input, two n-bit active operand outputs, one n-bit result output, and one instruction operand output;
each of the operative microcomputer modules having basic logic elements;
the basic logic elements each having at least two basic n-bit active operand registers, one basic n-bit result register with input and output data-stream routing devices built into the register, a multifunctional controllable combination logic unit with an instruction-assigned operating function, an instruction register, and a set of internal-data and instruction transfer buses;
the packet decoder having one control microinstruction address input and a plurality of outputs equal to a plurality of operative microcomputer modules in a computational cluster;
the network of local communications connecting buses having a first set of buses linking active operand inputs and outputs and the result operand outputs of each of the operative microcomputer modules with the active operand inputs and outputs and the result operand outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses; and
a second set of buses linking the control microinstruction inputs and outputs of each of the operative microcomputer modules with the control microinstruction inputs and outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses.
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Accused Products
Abstract
A dynamically reconfigurable distributed integrated circuit processor has at least one two-layer matrix in which a first layer has operative microcomputer modules (1) with local memory (2) grouped in computational clusters (5) and a second layer has a network of global communications connecting buses (7, 8) with packet decoders in coherence with the first layer. All components of the basic operating units are micro programmable and in universal communication selectively throughout separate operative microcomputer modules and throughout the computational clusters. Electrical conductivity of components is variable for select speed, timing and factors. A use method is described.
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Citations
14 Claims
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1. A dynamically reconfigurable distributed integrated circuit processor comprising:
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at least one two-layer integrated circuit matrix with a first layer and a second layer; the first layer having a plurality of operative microcomputer modules of computers distributed in one or more computational clusters and linked together by a network of local communications connecting buses; the second layer being a network of global communications connecting buses that are coherent with the first layer through at least one pathway batch controller proximate at least one network node of the global communications connecting buses; each of the operative microcomputer modules having at least three n-bit active operand inputs, one instruction input, two n-bit active operand outputs, one n-bit result output, and one instruction operand output; each of the operative microcomputer modules having basic logic elements; the basic logic elements each having at least two basic n-bit active operand registers, one basic n-bit result register with input and output data-stream routing devices built into the register, a multifunctional controllable combination logic unit with an instruction-assigned operating function, an instruction register, and a set of internal-data and instruction transfer buses; the packet decoder having one control microinstruction address input and a plurality of outputs equal to a plurality of operative microcomputer modules in a computational cluster; the network of local communications connecting buses having a first set of buses linking active operand inputs and outputs and the result operand outputs of each of the operative microcomputer modules with the active operand inputs and outputs and the result operand outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses; and a second set of buses linking the control microinstruction inputs and outputs of each of the operative microcomputer modules with the control microinstruction inputs and outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising the following steps for using a dynamically reconfigurable distributed integrated circuit processor:
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providing a dynamically reconfigurable distributed integrated circuit processor having at least one two-layer integrated circuit matrix with a first layer and a second layer, the first layer having a plurality of operative microcomputer modules of computers distributed in one or more computational clusters and linked together by a network of local communications connecting buses, the second layer being a network of global communications connecting buses that are coherent with the first layer through at least one packet decoder proximate at least one network node of the global communications connecting buses, and an injector for microcontrol peripheral communication with the global communications connecting buses; microprogramming the operative microcomputer modules such that select connections of data and instruction ports of at least a first operative microcomputer module has data and instruction ports that correspond selectively with data and instruction ports of at least a second operative microcomputer module in at least a first computational cluster of operative microcomputer modules; providing a select state of elevated electrical conductivity of the global communications buses and packet decoders of at least the first computational cluster of operative microcomputer modules during execution of selectively computational and logical operation by at least one select operative microcomputer module for at least one algorithm employed for the computational and logical operation by the at least one select operative microcomputer module; providing a select state of low electrical conductivity of other connections of the select operative microcomputer module with other processor elements during the execution of the selectively computational and logical operation by the at least one operative microcomputer module; and starting execution of microprogramming of operative microcomputer modules selectively for targeted application algorithms. - View Dependent Claims (8, 9, 10)
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11. A dynamically reconfigurable distributed integrated circuit processor comprising:
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at least one two-layer integrated circuit with a first layer and a second layer; the first layer having a plurality of operative microcomputer modules distributed in one or more computer clusters of operative microcomputer modules and linked together by a network of local communications connecting buses having generally orthogonal switchable intersections; the second layer being a network of global communication buses having generally orthogonal intersections that are coherent with the first layer through at least one pathway batch controller proximate at least one intersection of the global communication buses; wherein the first layer and the second layer have a generally planar distribution of the plurality of operative microcomputer modules, the one or more computational clusters of operative microcomputer modules, the network of local communications connecting buses with which the plurality of operative microcomputer modules are linked together and the network of global communication buses that are coherent with the first layer; wherein the operative microcomputer modules are generally rectangular with proximately adjoining corners in matrices of four or more that comprise computer clusters; wherein the at least one pathway batch controller is a plurality of pathway batch controllers proximate a plurality of intersections of the global communication buses that coincide with geometric centers of computer clusters; wherein each of the operative microcomputer modules have at least three n-bit active operand inputs, one instruction input, two n-bit active operand outputs, one n-bit result output, and one instruction operand output; and the global communications connecting buses having peripheral interface through at least one injector. - View Dependent Claims (12, 13, 14)
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Specification