Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device
First Claim
1. An integrated circuit including a digital processor that operates synchronously with respect to a periodic clock signal said digital processor coupled to a memory element external to said processor operable to access said external memory element in a given number of clock periods said digital processor including an instruction decode element, said instruction decode element comprising:
- a fetch unit for performing instruction fetches from said memory element requested from a decode unit of said instruction decode element, said fetch unit having a fetch program counter for storing addresses of said instruction fetches;
a decode unit coupled to said fetch unit for decoding instructions received from said memory element therein as a result of said instruction fetches, wherein said decode unit is operable to generate a "jump taken" signal to said fetch unit when a discontinuity is to occur in a given instruction fetch sequence, said jump taken signal indicative that fetching is to resume at a new value of said fetch program counter; and
a memory controller coupled to said fetch unit for performing fetch requests at given locations in said memory element, wherein said fetch unit is operable to generate an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request to the memory element, said outstanding memory request being terminated in fewer than said given number of clock periods in response to said abort signal.
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Abstract
The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a "jump taken" signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an "abort" signal to the memory controller. The memory controller unit interprets the abort signal to mean that the current memory access activity is to be terminated as soon as possible, such that aborting the current operation does not corrupt the stored content of the memory element. In addition to the abort signal, the memory controller unit may assert A "partial-done" signal that informs the fetch unit that some fraction of the current request has been completed. The size of the fractional data made available to the fetch unit will correspond to some size or alignment criteria such that the fetch unit may then be able to forward one instruction code to the decode unit. If the forwarded instruction is a "taken" jump, then the decode unit will be able to abort the current fetch request sooner than if it had to wait for the full request to be satisfied.
416 Citations
20 Claims
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1. An integrated circuit including a digital processor that operates synchronously with respect to a periodic clock signal said digital processor coupled to a memory element external to said processor operable to access said external memory element in a given number of clock periods said digital processor including an instruction decode element, said instruction decode element comprising:
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a fetch unit for performing instruction fetches from said memory element requested from a decode unit of said instruction decode element, said fetch unit having a fetch program counter for storing addresses of said instruction fetches; a decode unit coupled to said fetch unit for decoding instructions received from said memory element therein as a result of said instruction fetches, wherein said decode unit is operable to generate a "jump taken" signal to said fetch unit when a discontinuity is to occur in a given instruction fetch sequence, said jump taken signal indicative that fetching is to resume at a new value of said fetch program counter; and a memory controller coupled to said fetch unit for performing fetch requests at given locations in said memory element, wherein said fetch unit is operable to generate an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request to the memory element, said outstanding memory request being terminated in fewer than said given number of clock periods in response to said abort signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A digital processor device for use in a digital data processing system having external memory elements that operates synchronously with respect to a periodic clock signal, wherein access time to said external memory elements is substantially slower than access times to internal memory elements of said digital processor, said processor comprising:
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a fetch unit for performing instruction fetches requested from a decode unit of said digital processor to said external memory elements in a given number of clock periods, said fetch unit having a fetch program counter for storing addresses of said instruction fetches; and a decode unit coupled to said fetch unit for decoding instructions received therein as a result of said instruction fetches, wherein said decode unit is operable to generate a "jump taken" signal to said fetch unit when a discontinuity is to occur in a given instruction fetch sequence, said jump taken signal indicative that fetching is to resume at a new value of said fetch program counter, thereby causing any prefetched ones of said instruction fetches to be discarded; and wherein said decode element further includes a memory controller coupled to said fetch unit for performing fetch requests at given locations in said external memory elements, wherein said fetch unit is operable to generate an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request, whereby said outstanding memory request is terminated in fewer than said given number of clock periods in response to said abort signal. - View Dependent Claims (15, 16)
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17. A method of operating a digital processor in order to eliminate un-needed instruction fetches, said method comprising the steps of:
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transmitting instruction fetches requested by a decode unit of said digital processor from a fetch unit thereof to a memory controller; performing fetch requests at given locations in a memory element external to said digital processor by means of said memory controller in a given number of clock periods; decoding instructions received at said decode unit as a result of said instruction fetches; generating a "jump taken" signal to said fetch unit of said digital processor when a discontinuity is to occur in a given instruction fetch sequence; and generating an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request, whereby said outstanding memory request is terminated in fewer than said given number of clock periods in response to said abort signal. - View Dependent Claims (18, 19, 20)
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Specification