Logic circuit having error detection function, redundant resource management method and fault tolerant system using it

• US 6,092,217 A
• Filed: 11/03/1997
• Issued: 07/18/2000
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Hiroshi, Suzuki, Shoji, Kanekawa, Nobuyasu, Sato, Yoshimichi, Ohtsuji, Shinya, Tashiro, Korefumi, Nohmi, Makoto, Bekki, Keisuke
• Primary Examiner(s): HUA, LY
• Application Number:
  US08/962,879
• Time in Patent Office: 988 Days
• Field of Search: 364/488, 364/489, 364/491, 395/180, 395/182.01, 395/182.08, 395/182.09, 395/182.1, 395/182.11, 714/1, 714/4, 714/3, 714/10, 714/11, 714/12, 714/13
• US Class Current: 714/11
• CPC Class Codes: G05B 9/03 with multiple-channel loop, i.e. redundant control systems
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G06F 11/085 using codes with inherent redundancy, e.g. n-out-of-m codes
• CPC Class Codes: G06F 11/1695 which are operating with time diversity
• CPC Class Codes: G06F 11/18 using passive fault-masking of the redundant circuits error detection by comparing the output of redundant processing systems with continued operation after detection of the error G06F11/165
• CPC Class Codes: G06F 11/188 where exact match is not required
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits

Abstract

A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.

Claims

1. A redundant logic circuit or system that has function blocks which are provided with an identical function and are at least dualized, comprising:

means, responsive to an automatic logic synthesis or automatic wiring being carried out for said at least dualized function blocks, for generating N ways (n;

2 or greater integer) of logic or wiring patterns according to a design constraint that is changed as needed; and

means for selecting at least 2 ways of logic or wiring patterns from the generated ones according to a description of hardware description language.

2. The redundant logic circuit or system described in claim 1, wherein at least 2 ways of logic or wiring patterns are selected from the N ways of logic or wiring patterns generated according to the design constraint that is changed as needed so that a correlation function may be minimized, to assume the said at least dualized function blocks.

3. The redundant logic circuit or system described in claim 2, wherein the said correlation function is defined so that the status of the wiring net intersection may be affected in the correlation function.

4. The redundant logic circuit or system described in claim 2 or 3, wherein the said correlation function is defined as follows, ##EQU9## where, however, Φ

ijk must represent whether or not an intersection exists between wiring nets and be defined as follows, ##EQU10##

22. A fault tolerant system provided with first and second circuits comprising the redundant logical circuit described in claim 1, 13, or 14, or the fail-safe logical circuit described in claim 5 or 17 or the logical circuit with fault detecting function described in claim 9, 19, or 20, and a switching circuit that selects and outputs the output of either the said first circuit or the second circuit, wherein the said switching circuit selects the output according to an error detection signal from the said first or second logical circuit.

5. A fail-safe logic circuit or system that has function blocks which are provided with an identical function and are at least dualized and which provide an output to the external only when all the outputs from said function blocks match and stops the output or outputs an output to the external to guarantee safe side operation when outputs from the said function blocks do not match, comprising:

means, responsive to an automatic logic synthesis or automatic wiring being carried out for the said at-least dualized function blocks; and

means for generating N ways (n;

2 or greater integer) of logic or wiring patterns according to a design constraint that is changed as needed and for selecting at least 2 ways of logic or wiring patterns from the generated ones according to a description of hardware description language.

6. The fail-safe logic circuit or system described in claim 5, wherein at least 2 ways of logic or wiring patterns are selected from the N ways of logic or wiring patterns generated according to the design constraint that is changed as needed so that a correlation function may be minimized, to assume the said at least dualized function blocks.

7. The fail-safe logic circuit or system described in claim 6, wherein the said correlation function is defined so that the status of the wiring net intersection may be affected in the correlation function.

8. The fail-safe logic circuit or system described in claim 6 or 7, wherein the said correlation function is defined as follows, ##EQU11## where, however, Φ

ijk must represent whether or not an intersection exists between wiring nets and be defined as follows, ##EQU12##

9. A logic circuit or system with a fault detecting function, for function blocks which are provided with an identical function and are at least dualized, for detecting faults in the said function blocks, comprising:

means for comparing the outputs from the said function blocks; and

means, responsive to an automatic logic synthesis or automatic wiring being carried out for the said at-least dualized function blocks, for generating N ways (n;

2 or greater integer) of logic or wiring patterns according to a design constraint that is changed as needed and for selecting at least 2 ways of logic or wiring patterns from the generated ones according to a description of a hardware description language, to assume the said at-least dualized function blocks.

10. The logical circuit or system with fault detecting function described in claim 9, wherein at least 2 ways of logic or wiring patterns are selected from the N ways of logic or wiring patterns generated according to the design constraint that is changed as needed so that a correlation function may be minimized, to assume the said at-least dualized function blocks.

11. The logical circuit or system with fault detecting function described in claim 10, wherein the said correlation function is defined so that the status of the wiring net intersection may be affected in the correlation function.

12. The logical circuit or system with fault detecting function described in claim 10 or 11, wherein the said correlation function is defined as follows, ##EQU13## where, however, Φ

ijk must represent whether or not an intersection exists between wiring nets and be defined as follows, ##EQU14##

13. A redundant logical circuit or system, comprising:

function blocks which are provided with an identical function and are at least dualized; and

means for delaying the operations of each of said at least dualized function blocks by a certain time period (T delay), respectively.

15. The redundant logical circuit or system described in claims 13 or 14, wherein the said T delay value is an odd multiple of a half-cycle of the clock.

14. A redundant logical circuit or system that has function blocks which are provided with an identical function and are at least dualized, comprising:

means for delaying a signal or clock to be supplied to the first function block of the said at-least dualized function blocks by a certain time period (T delay); and

means for delaying a signal to be output from the second function block by a certain time period (T delay) and for comparing said output signal with the output from the first function block.

16. A fail-safe logic circuit or system that has function blocks which are provided with an identical function and are at least dualized, comprising:

means for supplying an output to the external only when all the outputs from said function blocks match and for stopping supply of an output to the external to guarantee safe side operation when outputs from the said function blocks do not match; and

means for delaying the operations of the said at-least dualized function blocks by a certain time period (T delay), respectively.

18. The fail-safe logic circuit or system described in claims 16 or 17, wherein the said T delay value is an odd multiple of a half-cycle of the clock.

17. A fail-safe logic circuit or system that has function blocks which are provided with an identical function and are at least dualized, comprising:

means for supplying an output to the external only when all the outputs from said each of said function blocks match and for stopping supply of an output to the external to guarantee safe side operation when outputs from each of said function blocks do not match;

means for delaying a signal or clock to be supplied to the first function block of the said at least dualized function blocks by a certain time period (T delay); and

#

means for delaying a signal to be output from the second function block of said dualized function blocks by a certain time period (T delay) and for comparing said output signal with the output from the first function block.

19. A logical circuit or system comprising:

fault detecting means, provided for function blocks which are provided with an identical function and are at least dualized, for detecting faults in the said at-least dualized function blocks by comparing outputs from both of the said at-least dualized function blocks; and

means for delaying operations of each of said at-least dualized function blocks by a certain time period (T delay), respectively.

21. A logical circuit or system with a fault detecting function as described in claims 19 or 20, wherein the said T delay value is an odd multiple of a half-cycle of the clock.

20. A logical circuit or system with a fault detecting function, for function blocks which are provided with an identical function and are at least dualized, for detecting faults in the said function blocks by comparing outputs from both of the said at-least dualized function blocks, comprising:

means for delaying a signal or clock nsupplied to the first function block of the said at-least dualized function blocks by a certain time period (T delay); and

means for delaying a signal output from the second function block by a certain time period (T delay) and for comparing the output signal with the output from the first function block.

23. A redundant logical circuit or system, comprising:

function blocks which are provided with an identical function and are at least dualized; and

means for providing diversity so that faults detected in one of the said at least dualized function blocks will not affect the operation of others of said at least dualized function blocks.

24. A redundant logical circuit or system according to claim 23 wherein said means for providing diversity comprises:

means for delaying the operations of the said at least dualized function blocks by a certain time period (T delay), respectively.

25. A redundant logical circuit or system, comprising:

function blocks which are provided with an identical function and are at least dualized; and

means for providing diversity so that faults detected in one of the said at least dualized function blocks will not affect the operation of others of said at least dualized function blocks,

wherein said means for providing diversity comprises;

means, responsive to a automatic logic synthesis or automatic wiring being carried out for said at least dualized function blocks, for generating N ways (n;

2 or greater integer) of logic or wiring patterns according to a design constraint that is changed as needed; and

means for selecting at least 2 ways of logic or wiring patterns from the generated ones according to a description of hardware description language.

26. A redundant logical circuit or system, comprising:

function blocks which are provided with a same program and said function blocks are at least dualized; and

means for delaying the operations of the said at least dualized function blocks by a certain time period (T delay), respectively.

27. A redundant logical circuit or system, comprising:

function blocks which are provided with an identical function and said function blocks are at least dualized; and

means for delaying the operations of the said at least dualized function blocks by 1/2 clock, in order to improve the error detection rate.