Test circuit

• US 6,092,227 A
• Filed: 02/05/1998
• Issued: 07/18/2000
• Est. Priority Date: 09/19/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric System (Mitsubishi Electric Corporation)
• Inventors: Saitoh, Tsuyoshi, Toki, Hideki, Kitaguchi, Akira, Hatakenaka, Makoto, Matsuo, Masaaki, Shiroshima, Kiyoyuki
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/018,934
• Time in Patent Office: 894 Days
• Field of Search: 714/718, 714/719, 714/736, 714/42, 714/54, 714/820, 365/200, 365/201
• US Class Current: 714/736
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.

Claims

1. A test circuit comprising:

a memory device;

data writing means for outputting m-bit data immediately after the m-bit data is captured from an input/output terminal of said data writing means in response to a clock signal, branching the m-bit data to n identical m-bit signals, and writing the n m-bit data signals into said memory device;

function determining means for reading the n m-bit data signals written into said memory device, outputting one of the n m-bit data signals read from said memory device, comparing the one m-bit data signal read from said memory device to an m-bit expected value, and determining coincidence or non-coincidence between the one m-bit data signal read from said memory device and the m-bit expected value; and

a wide data bus connected to said data writing means, said memory device, and said function determining means for transferring the n m-bit data signals between said data writing means, said memory device, and said function determining means.

2. The test circuit according to claim 1, wherein said data writing means comprises:

a D flip-flop for capturing the m-bit data from the input/output terminal of said data writing means in response to the clock signal and immediately outputting the captured m-bit data; and

a data line for branching the m-bit data output from said D flip-flop into n identical m-bit data signals, said function determining means comprises;

a selected data output unit for outputting one of the n m-bit data signals read from said memory device to n input/output terminal of said selected data output unit based on a selection signal; and

a coincidence/non-coincidence determining unit for determining coincidence or non-coincidence between the n m-bit data signals read from said memory device and the n m-bit data signals written into said memory device and monitoring the coincidence/non-coincidence, and said wide data bus is connected to n data lines carrying the n m-bit data signals, said memory device, said selected data output unit, and said coincidence/non-coincidence determining unit for transferring the n m-bit data signals between the n data lines, said memory device, and said selected data output unit.

3. The test circuit according to claim 2, comprising test pattern generating means for generating test patterns for detecting a failure in said coincidence/non-coincidence determining unit and transferring the generated test patterns to said coincidence/non-coincidence determining unit through said wide data bus.