Modified dual damascene process

• US 6,093,632 A
• Filed: 12/07/1998
• Issued: 07/25/2000
• Est. Priority Date: 12/07/1998
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lin, Kang-Cheng
• Primary Examiner(s): Dinh, Son T.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US09/206,738
• Time in Patent Office: 596 Days
• Field of Search: 438/618, 438/637, 438/700, 438/626, 438/624, 438/701, 438/702, 438/640, 438/667, 438/622
• US Class Current: 438/618
• CPC Class Codes: H01L 21/7681 involving one or more buried masks

Abstract

A process for creating a metal filled, dual damascene opening, in a composite insulator layer, has been developed. The process features selective RIE procedures, used to create a wide diameter opening in an upper silicon oxide layer, and a narrow diameter opening in a lower silicon oxide layer. Small area, silicon nitride islands, or shapes, a component of the composite insulator layer, are used as a stop layer, during the selective RIE procedures. The use of small area, silicon nitride shapes, offers less composite insulator capacitance, than counterparts fabricated using larger area, silicon nitride stop layers.

Claims

1. A method of fabricating a metal structure, on a semiconductor substrate, with the metal structure featuring a wide, metal shape, on underlying, narrow metal shape, comprising the steps of:

providing a first metal interconnect structure, located in an opening in a first insulator layer;

depositing a first silicon nitride layer, a second insulator layer, and a second silicon nitride layer, on the top surface of said first metal interconnect structure, and on the top surface of said first insulator layer;

patterning of said second silicon nitride layer, to form silicon nitride islands, with narrow spaces between said silicon nitride islands, exposing a portion of the top surface of underlying, said second insulator layer;

depositing a third insulator layer;

forming a photoresist shape, on said third insulator layer, featuring a wide opening in said photoresist shape, exposing a portion of the top surface of said third insulator layer;

performing a selective, first dry etching procedure, using said wide opening, in said photoresist shape as a mask, to create a wide diameter opening, in said third insulator layer, exposing a portion of said silicon nitride islands, and exposing a narrow space, located between said silicon nitride islands, then continuing said selective, first dry etching procedure, to create a narrow diameter opening in said second insulator layer, using portions of said silicon nitride islands, exposed in said wide diameter opening, as a mask, to create a narrow diameter opening in said second insulator layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening;

performing a selective, second dry etching procedure, to remove portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure, and removing portions of said silicon nitride islands, exposed in said wide diameter opening; and

forming said metal structure, comprised of said wide metal shape, located in said wide diameter opening, and comprised of said narrow metal, located in said narrow diameter opening, with said narrow metal shape, overlying and contacting, the portion of said first metal interconnect structure, exposed at the bottom of said narrow diameter opening.

2. The method of claim 1, wherein said first silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 300 Angstroms.

3. The method of claim 1, wherein said second insulator layer is silicon oxide, obtained via LPCVD or PECVD procedures, at a thickness between about 4000 to 15000 Angstroms.

4. The method of claim 1, wherein said second silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 2000 Angstroms.

5. The method of claim 1, wherein said silicon nitride islands are formed via an anisotropic RIE procedure, performed to said second silicon nitride layer, using a fluorine based gas, such as CHF₃, CH₂ F₂, or CH₃ F, as an etchant, with a space between said silicon nitride islands, of at least 500 Angstroms.

6. The method of claim 1, wherein said third insulator layer is silicon oxide, obtained via LPCVD or PECVD procedures, at a thickness between about 3000 to 15000 Angstroms.

7. The method of claim 1, wherein said selective, first dry etching procedure, used to create said wide diameter opening, in said third insulator layer, and to create said narrow diameter opening, in said second insulator layer, is an anisotropic RIE procedure, using CHF₃ as an etchant.

8. The method of claim 1, wherein the diameter of said wide diameter opening, in said third insulator layer, is between about 1500 to 10000 Angstroms.

9. The method of claim 1, wherein the diameter of said narrow diameter opening, in said second insulator layer, is between about 1500 to 5000 Angstroms.

10. The method of claim 1, wherein said selective, second dry etching procedure, used to remove the portion of said first silicon nitride layer, exposed in said narrow diameter opening, and to remove the portions of said silicon nitride islands, exposed in said wide diameter opening, is an anisotropic RIE procedure, using a fluorine based gas, such as CHF₃, CH₂ F₂, or CH₃ F, as an etchant.

11. The method of claim 1, wherein said metal structure, formed in said wide diameter opening, and in said narrow diameter opening, is comprised of copper.

12. A method of forming a metal structure, on a semiconductor substrate, comprised of a wide metal shape, on an underlying narrow metal shape, using a dual damascene process, and using silicon nitride islands as an etch stop, during the patterning of a dual damascene opening, in a composite insulator layer, comprising the steps of:

providing a first silicon oxide layer, with an opening in said first silicon oxide layer;

forming a first metal interconnect structure, in said opening in said first silicon oxide layer;

depositing a first silicon nitride layer;

depositing a second silicon oxide layer;

depositing a second silicon nitride layer;

patterning of said second silicon nitride layer, to create said silicon nitride islands, on said second silicon oxide layer, and creating a narrow space between said silicon nitride islands, exposing a portion of the top surface of said second silicon oxide layer;

depositing a third silicon oxide layer;

forming a photoresist shape, with a wide diameter opening in said photoresist shape, exposing a portion of the top surface of said third silicon oxide layer;

performing a selective, first RIE procedure, using said wide diameter opening, in said photoresist shape, as a mask, to create a wide diameter opening, in said third silicon oxide layer, than using portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, as a mask, to create a narrow diameter opening, in said second silicon oxide layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening;

performing a selective, second RIE procedure, removing said portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, and removing said portion of said first silicon nitride layer, exposed at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure;

depositing a metal layer; and

removing portions of metal layer from the top surface of said third silicon oxide layer, forming said metal structure in said dual damascene opening, with said metal structure comprised of a wide metal shape, located in said wide diameter opening, and comprised of a narrow metal shape, located in said narrow diameter opening.

13. The method of claim 12, wherein said first metal interconnect structure is comprised of a titanium titanium--nitride, adhesive--barrier layer, on the sides of said opening in said first silicon oxide layer, and filled with copper.

14. The method of claim 12, wherein said first silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 300 Angstroms.

15. The method of claim 12, wherein said second silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 4000 to 15000 Angstroms.

16. The method of claim 12, wherein said second silicon nitride layer is obtained via LPCVD or PECVD procedures. at a thickness between about 200 to 2000 Angstroms.

17. The method of claim 12, wherein said silicon nitride islands are formed via an anisotropic RIE procedure, applied to said second silicon nitride layer, using a fluorine based gas, such as CH₃ F, CHF₃, or CH₂ F₂, as an etchant.

18. The method of claim 12, wherein said narrow space, between said silicon nitride islands, is at least 500 Angstroms.

19. The method of claim 12, wherein said third silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 3000 to 15000 Angstroms.

20. The method of claim 12, wherein said selective, first RIE procedure, used to create said wide diameter opening, in said third silicon oxide layer, and to create said narrow diameter opening, in said second silicon oxide layer, is performed using CHF₃ as an etchant.

21. The method of claim 12, wherein the diameter of said wide diameter opening, in said third silicon oxide layer, is between about 1500 to 10000 Angstroms.

22. The method of claim 12, wherein the diameter of said narrow diameter opening, in said second silicon oxide layer, is between about 1500 to 5000 Angstroms.

23. The method of claim 12, wherein said selective, second RIE procedure, used to remove said portion of said silicon nitride, exposed in said wide diameter opening, and used to remove the portion of said first silicon nitride layer, exposed at the bottom of said narrow diameter opening, is performed using a fluorine based such as CHF₃, CH₂ F₂, or CH₃ F, as an etchant.

24. The method of claim 12, wherein said metal structure, formed in said dual damascene opening, is comprised of a titanium -titanium nitride, adhesive--barrier layer, on the sides of said dual damascene opening, and comprised of a copper layer, located inside the dual damascene opening.