CMOS logic circuit and method of driving the same

• US 6,094,068 A
• Filed: 06/18/1998
• Issued: 07/25/2000
• Est. Priority Date: 06/19/1997
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nomura, Masahiro, Yamashina, Masakazu
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/098,307
• Time in Patent Office: 768 Days
• Field of Search: 326/86, 326/83, 326/112, 326/119, 326/121, 326/17, 326/15, 327/534
• US Class Current: 326/83
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.

Claims

1. A CMOS logic circuit comprising:

(a) a PMOS transistor;

(b) an NMOS transistor;

(c) a first coupling capacitor electrically connected between a gate and a drain of said PMOS transistor; and

(d) a second coupling capacitor electrically connected between a gate and a drain of said NMOS transistor,

said PMOS and NMOS transistors including substrates, voltages of which are made higher than associated reference voltages at rise edges of signals transmitted to said gates, and made lower than said associated reference voltages at fall edges of said signals.

2. The CMOS logic circuit as set forth in claim 1, wherein gates of said PMOS and NMOS transistors are electrically connected to each other and drains of said PMOS and NMOS transistors are electrically connected to each other, and wherein an input signal is introduced into the thus electrically connected gates and an output signal is taken through the thus electrically connected drains.

3. The CMOS logic circuit as set forth in claim 1, wherein each of said first and second coupling capacitors comprises a PN junction capacitor formed between a respective one of said substrates having a first conductivity type and a respective diffusion region having a second conductivity type in said substrate.

4. The CMOS logic circuit as set forth in claim 1, wherein each of said first and second coupling capacitors comprises a gate insulating film.

5. The CMOS logic circuit as set forth in claim 1, wherein said CMOS logic circuit comprises a plurality of PMOS and NMOS transistors, wherein a plurality of diffusion regions formed between said plurality of PMOS and NMOS transistors have the same conductivity type as that of an associated substrate of said plurality of PMOS and NMOS transistors, and wherein a constant bias voltage is applied to each type of said plurality of diffusion regions.

6. The CMOS logic circuit as set forth in claim 1, wherein said CMOS logic circuit further comprises a substrate having a silicon-on-insulator (SOI) structure.

7. The CMOS logic circuit as set forth in claim 1, wherein each of said first and second coupling capacitors comprises a MOS gate capacitor.

8. A CMOS logic circuit comprising:

(a) a PMOS transistor;

(b) an NMOS transistor;

(c) a first coupling capacitor electrically connected between a gate and a drain of said PMOS transistor; and

(d) a second coupling capacitor electrically connected between a gate and a drain of said NMOS transistor,

said PMOS transistor being designed and adapted to have a higher threshold voltage and said NMOS transistor being designed and adapted to have a lower threshold voltage than an associated reference voltage at rising edges of signals transmitted to gates of said PMOS and NMOS transistors, and

said PMOS transistor being designed and adapted to have a lower threshold voltage and said NMOS transistor being designed and adapted to have a higher threshold voltage than an associated reference voltage at falling edges of signals transmitted to gates of said PMOS and NMOS transistors.

9. A CMOS NAND logic circuit comprising:

(a) a first PMOS transistor;

(b) a second PMOS transistor;

(c) a first NMOS transistor;

(d) a second NMOS transistor;

(e) a first coupling capacitor electrically connected between a gate and a drain of said first PMOS transistor;

(f) a second coupling capacitor electrically connected between a gate and a drain of said second PMOS transistor;

(g) a third coupling capacitor electrically connected between a gate and a drain of said first NMOS transistor;

(h) a fourth coupling capacitor electrically connected between a gate and a drain of said second NMOS transistor,

said first and second PMOS and NMOS transistors including substrates, voltages of which are made higher than associated reference voltages at rising edges of signals transmitted to said gates, and made lower than said associated reference voltages at falling edges of said signals.

10. The CMOS NAND logic circuit as set forth in claim 9, wherein gates of said first PMOS and said first NMOS transistors are electrically connected to each other, drains of said first and said second PMOS and said first NMOS transistors are electrically connected to each other to provide an output signal, and gates of said second PMOS and said second NMOS transistors are electrically connected to each other, and wherein a first input signal is provided to said gates of said first PMOS and said first NMOS transistors, and a second input signal is provided to said gates of said second PMOS and said second NMOS transistors.

11. The CMOS NAND logic circuit as set forth in claim 10, wherein a source of said first NMOS transistor and a drain of said second NMOS transistor are electrically connected to each other.

12. The CMOS NAND logic circuit as set forth in claim 9, wherein each of said first through fourth coupling capacitors comprises a PN junction capacitor between a respective one of said substrates and a respective diffusion region in said substrate.

13. The CMOS NAND logic circuit as set forth in claim 9, wherein each of said first through fourth coupling capacitors comprises a gate insulating film.

14. The CMOS NAND logic circuit as set forth in claim 9, further comprising a plurality of PMOS and NMOS transistors, wherein a plurality of diffusion regions between said PMOS and NMOS transistors have the same conductivity type as that of an associated substrate of each of said PMOS and NMOS transistors, and wherein a constant bias voltage is applied to each of said diffusion regions.

15. The CMOS NAND logic circuit as set forth in claim 9, wherein each of said substrates have a silicon-on-insulator (SOI) structure.

16. The CMOS NAND logic circuit as set forth in claim 9, wherein each of said first and second coupling capacitors comprises a MOS gate capacitor.

17. A CMOS NAND logic circuit comprising:

(a) a first PMOS transistor;

(b) a second PMOS transistor;

(c) a first NMOS transistor;

(d) a second NMOS transistor;

(e) a first coupling capacitor electrically connected between a gate and a drain of said first PMOS transistor;

(f) a second coupling capacitor electrically connected between a gate and a drain of said second PMOS transistor;

(g) a third coupling capacitor electrically connected between a gate and a drain of said first NMOS transistor; and

(h) a fourth coupling capacitor electrically connected between a gate and a drain of said second NMOS transistor,

said first and second PMOS and NMOS transistors being designed and adapted to have a higher threshold voltage, and each of said first and second NMOS transistors being designed and adapted to have a lower threshold voltage than an associated reference voltage at rising edges of signals transmitted to gates of said first and second PMOS and NMOS transistors, and

said first and second PMOS transistors being designed and adapted to have a lower threshold voltage, and said first and second NMOS transistors being designed and adapted to have a higher threshold voltage than an associated reference voltage at falling edges of signals transmitted to gates of said first and second PMOS and NMOS transistors.

18. A method of driving a CMOS logic circuit including:

(a) a PMOS transistor;

(b) an NMOS transistor;

(c) a first coupling capacitor electrically connected between a gate and a drain of said PMOS transistor; and

(d) a second coupling capacitor electrically connected between a gate and a drain of said NMOS transistor, comprising the steps of;

providing voltages at substrates of said PMOS and NMOS transistors, which voltages are higher than associated reference voltages during time intervals when a leading edge of an input signal is transmitted to said gates; and

providing voltages at the substrates of each of the PMOS and NMOS transistors which are lower than the associated reference voltages during time intervals when a trailing edge of an input signal is transmitted to the gates.

19. The method as set forth in claim 18, further comprising the steps of:

introducing an input signal into the gates of the PMOS and NMOS transistors; and

taking an output signal through the drains of the PMOS and NMOS transistors.

20. A method of driving a CMOS logic circuit including:

(a) a PMOS transistor;

(b) an NMOS transistor;

(c) a first coupling capacitor electrically connected between a gate and a drain of said PMOS transistor; and

(d) a second coupling capacitor electrically connected between a gate and a drain of said NMOS transistor, the method comprising the steps of;

developing a threshold voltage of said PMOS transistor higher and a threshold voltage of said NMOS transistor lower than an associated reference voltage during a time interval when a leading edge of an input signal is transmitted to the gates of said PMOS and NMOS transistors, and

developing the threshold voltage of said PMOS transistor lower and the threshold voltage of said NMOS transistor higher than the associated reference voltage during a time interval when a trailing edge of an input signal is transmitted to the gates of the PMOS and NMOS transistors.

21. A method of driving a CMOS NAND logic circuit including:

(a) a first PMOS transistor;

(b) a second PMOS transistor;

(c) a first NMOS transistor;

(d) a second NMOS transistor;

(e) a first coupling capacitor electrically connected between a gate and a drain of said first PMOS transistor;

(f) a second coupling capacitor electrically connected between a gate and a drain of said second PMOS transistor;

(g) a third coupling capacitor electrically connected between a gate and a drain of said first NMOS transistor; and

(h) a fourth coupling capacitor electrically connected between a gate and a drain of said second NMOS transistor, the first PMOS and the first NMOS transistors having respective gates connected together for receiving a first input signal, the second PMOS and the second NMOS transistors having respective gates connected together for receiving a second input signal, the first and second PMOS transistors and the first NMOS transistor having respective drains connected together for providing an output signal, the second NMOS transistor having a drain connected to a source of the first NMOS transistor, the method comprising the steps of;

providing voltages at the substrates of said first and second PMOS and NMOS transistors, which voltages are higher than associated reference voltages during a time interval when a leading edge of an input signal is transmitted to said gates; and

providing voltages at the substrates of each of the first and second PMOS and NMOS transistors, which voltages are lower than said associated reference voltages during time intervals when a trailing edge of an input signal is transmitted to the gates.

22. The method as set forth in claim 21, further comprising the steps of:

introducing a first input signal into the electrically connected gates of said first PMOS and the first NMOS transistors;

introducing a second input signal into the electrically connected gates of said second PMOS and second NMOS transistors; and

taking an output signal from the electrically connected drains of said first and second PMOS transistors and the first NMOS transistor.

23. A method of driving a CMOS NAND logic circuit including:

(a) a first PMOS transistor;

(b) a second PMOS transistor;

(c) a first NMOS transistor;

(d) a second NMOS transistor;

(e) a first coupling capacitor electrically connected between a gate and a drain of said first PMOS transistor;

(f) a second coupling capacitor electrically connected between a gate and a drain of said second PMOS transistor;

(g) a third coupling capacitor electrically connected between a gate and a drain of said first NMOS transistor; and

(h) a fourth coupling capacitor electrically connected between a gate and a drain of said second NMOS transistor, the first and second PMOS transistors and the first NMOS transistor having respective drains connected together for providing an output signal, the second NMOS transistor having a drain connected to a source of the first NMOS transistor for providing an intermediate signal, the method comprising the steps of;

developing a threshold voltage of said first and second PMOS transistors higher and a threshold voltage of said first and second NMOS transistors lower than an associated reference voltage during a time interval when a leading edge of an input signal is transmitted to the gates of said first and second PMOS and the first and second NMOS transistors, and

developing the threshold voltage of said first and second PMOS transistors lower and the threshold voltage of said first and second NMOS transistors higher than the associated reference voltage during a time interval when a trailing edge of an input signal is transmitted to the gates of said first and second PMOS and the first and second NMOS transistors.