×

High speed common mode logic circuit

  • US 6,094,074 A
  • Filed: 07/16/1998
  • Issued: 07/25/2000
  • Est. Priority Date: 07/16/1998
  • Status: Expired due to Term
First Claim
Patent Images

1. A logic circuit, comprising:

  • a bias circuit having a first pair of MOS transistors and a third MOS transistor, wherein one of said first pair of transistors has an aspect ratio greater than an aspect ratio of the other of the first pair of transistors causes said third MOS transistor to operate in a triode region; and

    a logic portion having a plurality of pairs of input MOS transistors, and a plurality of load MOS transistors, a respective one of which is coupled to each pair of input MOS transistors, wherein said bias circuit causes each of the load MOS transistors to operate in the triode region.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×