High speed common mode logic circuit

• US 6,094,074 A
• Filed: 07/16/1998
• Issued: 07/25/2000
• Est. Priority Date: 07/16/1998
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Chi, Kuang-Kai, Xu, Ping
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/116,645
• Time in Patent Office: 740 Days
• Field of Search: 326/54, 326/55, 326/115, 326/112, 326/119, 326/121, 327/307, 327/208
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W_P /L_P) and the other of which has an aspect ratio (W_P /L_P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the bias circuit to operate exclusively in the triode region. The CML circuit also includes a logic portion, which may be a logic gate or flip-flop, having a plurality of pairs of input MOS transistors for receiving differential input signals. In accordance with the invention, the logic portion has load MOS transistors which operate exclusively in the triode region.

Claims

1. A logic circuit, comprising:

a bias circuit having a first pair of MOS transistors and a third MOS transistor, wherein one of said first pair of transistors has an aspect ratio greater than an aspect ratio of the other of the first pair of transistors causes said third MOS transistor to operate in a triode region; and

a logic portion having a plurality of pairs of input MOS transistors, and a plurality of load MOS transistors, a respective one of which is coupled to each pair of input MOS transistors, wherein said bias circuit causes each of the load MOS transistors to operate in the triode region.

2. The logic circuit of claim 1, wherein said first pair of MOS transistors are configured such that one of said first pair of MOS transistors has an aspect ratio (W_P /L_P) and the other of said first pair of MOS transistors has an aspect ratio (W_P /L_P)/n, wherein 1<

n<

4.

3. The logic circuit of claim 1, wherein said bias circuit further comprises a plurality of current mirror MOS transistors which cooperate to generate a reference current.

4. The logic circuit of claim 1, wherein said plurality of input MOS transistors includes first and second pairs of input MOS transistors for receiving a first differential input signal.

5. The logic circuit of claim 4, wherein said plurality input MOS transistors further includes a third pair of input MOS transistors for receiving a second differential input signal.

6. The logic circuit of claim 5, wherein said bias circuit generates a bias voltage that is applied to a gate of each of said load MOS transistors.

7. The logic circuit of claim 6, wherein the bias voltage is generated at a gate of said third MOS transistor of said bias circuit.

8. The logic circuit of claim 1, wherein said logic portion comprises a logic gate.

9. The logic circuit of claim 8, wherein said logic gate is selected from the group consisting of AND, OR, inverter, NAND, NOR, XOR and XNOR.

10. The logic circuit of claim 1, wherein said logic portion comprises a flip-flop.

11. The logic circuit of claim 10, wherein said flip-flop is selected from the group consisting of RS flip-flop, D-flip-flop, JK flip-flop and T flip-flop.