Circuit for configuring data and energy parameters in a multi-channel communications system
First Claim
1. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a system data rate R using N sub-channels, said circuit comprising:
- a sub-channel parameter memory for storing K signal-to-noise associated with K sub-channels, where K≦
N; and
a processing unit for determining data capacities of each of the K sub-channels based on an evaluation of the following parameters;
i) the K signal-to-noise values; and
ii) said system data rate R; and
iii) a number Nch of the K sub-channels having a non-zero bit capacity; and
wherein the processing unit determines the data capacities in one or more iterations of a routine executed by the processing unit, and Nch is calculated during each iteration.
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Accused Products
Abstract
A circuit for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (NCH) from iteration to iteration, which results in a more accurate loading of the sub-channels. If adjustments to bit loadings are required to achieve a particular initial target rate, the circuit first adjusts those sub-channels which will have the least effect on the overall system performance margin, so that compliance with system requirements is better achieved. In addition, an "iteration criteria" count can be incorporated to ensure that the initialization of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.
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Citations
76 Claims
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1. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a system data rate R using N sub-channels, said circuit comprising:
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a sub-channel parameter memory for storing K signal-to-noise associated with K sub-channels, where K≦
N; anda processing unit for determining data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise values; and ii) said system data rate R; and iii) a number Nch of the K sub-channels having a non-zero bit capacity; and wherein the processing unit determines the data capacities in one or more iterations of a routine executed by the processing unit, and Nch is calculated during each iteration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a target data rate R using K sub-channels, said circuit comprising:
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a sub-channel parameter memory for storing K signal-to-noise values associated with K sub-channels, where K<
N; anda processing unit for determining data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise values; and ii) said target data rate R; and iii) an iteration criteria count M; and wherein the processing unit can determine the data capacities in M or fewer iterations of a configuration routine. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a system data rate R using K sub-channels, and said system being coupled to a transmission channel having varying transmission characteristics, said circuit comprising:
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a sub-channel parameter memory for storing signal to noise values associated with some or all of said sub-channels; and a processing unit which can perform a configuration procedure to configure said system to operate at said system data rate R; and wherein the configuration procedure includes operations executed by the processing unit in one or more iterations, and during each iteration a sub-channel usability determination is made of which of the K sub-channels should be disabled, such determination being based on a consideration of a calculated minimum (bmin) and maximum (bmax) bit capacity of said sub-channels; and further wherein the processing unit allocates bit loadings only to the sub-channels which are not disabled during each iteration. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a system target data rate R using K sub-channels and with an overall target output power value P through a channel having varying transmission characteristics, said circuit comprising:
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a sub-channel parameter memory for storing signal to noise values associated with some or all of said sub-channels; and a processing unit which can perform a configuration procedure to configure said system to operate at said system target data rate R; and wherein the configuration procedure includes operations executed by the processing unit in one or more iterations, and during each iteration; i) a determination is made of a proposed minimum (bmin) and a proposed maximum (bmax) bit loading for the data capacities of sub-channels that are not disabled; and ii) a determination is made of an output power value P'"'"' associated with such proposed loading; and iii) if P'"'"'>
P, bit capacity is removed in sorted order from those sub-channels which have the greatest power differential associated with carrying either bmin or bmax until P'"'"'=P. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a system data rate R through a channel having varying transmission characteristics, and said system using K sub-channels, a total transmission power P, and a power margin γ
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m, said circuit comprising;
a sub-channel parameter memory for storing signal to noise values with some or all of said sub-channels; and a processing unit which can perform a configuration procedure to configure data capacities; and wherein the configuration procedure includes operations executed by the processing unit to compute a rate Btotal based on the following; i) a determination of a proposed minimum (bmin) and a proposed maximum (bmax) bit loading for the data capacities of sub-channels that are not disabled; and ii) a determination of an output power value P'"'"' and power modification factors, emax and emin associated with such bit loadings; and iii) replacing bmax with bmin, and emax with emin, for one or more sub-channels, until P'"'"'≦
P;whereby Btotal =Σ
bmax for all the sub-channels, and is maximized for such values of P and γ
m. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
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m, said circuit comprising;
Specification