Security apparatus for data transmission with dynamic random encryption

• US 6,094,486 A
• Filed: 07/23/1999
• Issued: 07/25/2000
• Est. Priority Date: 06/19/1997
• Status: Expired due to Fees

• Current Assignee: Brian E. Marchant
• Original Assignee: Brian E. Marchant
• Inventors: Marchant, Brian E.
• Primary Examiner(s): Hayes, Gail O.
• Assistant Examiner(s): Tucker, Christopher M.
• Application Number:
  US09/359,857
• Time in Patent Office: 368 Days
• Field of Search: 713/172, 380/52, 380/264, 380/28, 380/45, 380/42, 711/219, 711/220, 711/202, 711/209, 707/9, 707/100
• US Class Current: 380/52
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/128 involving web programs, i.e. using technology especially used in internet, generally interacting with a web browser, e.g. hypertext markup language [HTML], applets, java
• CPC Class Codes: G06F 21/6272 by registering files or documents with a third party
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2211/001 In-Line Device
• CPC Class Codes: G06F 2211/008 Public Key, Asymmetric Key, Asymmetric Encryption

Abstract

A security apparatus including a number input device (302), an address register (312) responsive to the number input device, an encryption schema memory (316) addressable by the address register to produce an output code and a relative address code, and address incrementing logic (310) responsive the relative address code and operative to increment the address register. The apparatus also preferably includes a PIN register (304) coupled to the number input device, a public code register (306) coupled to the number input device, and merging logic (308) merging outputs of the PIN register and the public code register to be input to the address register. The apparatus also preferably includes an output shift register operative to shift out the output code of the encryption schema memory. The encryption schema memory can be read only memory, writeable memory, or both.

Claims

1. A security apparatus comprising;

a number input device;

an address register responsive to said number input device;

an encryption schema memory storing an encryption schema including a random array of bits, said on schema memory addressable by said address register to produce both an output code including a length of spring identifier and an encryption algorithm identifier, and a relative address code; and

address incrementing logic responsive to said relative address code and operative to increment said address register,

whereby said encryption algorithm identifier identifies a particular encryption algorithm utilized to encrypt a set of data having a length defined by said length of string identifier.

2. A security apparatus as recited in claim 1 further comprising:

a PIN register coupled to said number input device;

a public code register coupled to said number input device; and

merging logic merging outputs of said PIN register and said public code register to be input to said address register.

3. A security apparatus as recited in claim 2 further comprising an output shift register operative to shift out said output code of said encryption schema memory.

4. A security apparatus as recited in claim 1, wherein said encryption schema memory is read only memory.

5. A security apparatus as recited in claim 1, wherein said encryption schema memory includes a writeable memory.

6. A security apparatus as recited in claim 1 wherein said random array of bits consists of 1M bits of random information.

7. A security apparatus as recited in claim 1 wherein said length of said data set defined by said length of string identifier is randomly determined.

8. A security apparatus as recited in claim 7 wherein said length of said data set although random is no greater than a predefined length.

9. A security apparatus as recited in claim 1 wherein said security apparatus is a portable device which when in operation must be coupled to a host computer system said host computer performing said encryption utilizing said output code, whereby security is enhanced as the identification of said particular encryption algorithm utilized and said length of said data set encryted by said particular encryption algorithm is determined by said security apparatus which being a device separate from said host computer system decreases risks of security attacks.

10. A security apparatus as recited in claim 6 wherein security apparatus plugs into a peripheral device port of said host computer system.

11. A security apparatus as recited in claim 7 wherein said peripheral device port is a mouse port.

12. A security apparatus as recited in claim 6 wherein said security apparatus is operable to draw any needed power from said host computer system.

13. A security apparatus as recited in claim 1 wherein said number input device is an electro-mechanical device manually actuated to enter a sequence of numbers.

14. A security apparatus as recited in claim 10 wherein said electro-mechanical device includes a plurality of number wheels.

15. A security apparatus as recited in claim 1 wherein said number input device is an electronic input device.

16. A security apparatus comprising:

a processor;

a plurality of memories coupled to said processor, where each memory stores an encryption schema including a random array of bits;

a number input device coupled to said processor to at least partially provide a starting address for at least one of said plurality of memories; and

an address register process executing on said processor, said address register process maintaining an address register variable initially storing said starting address, said address register process operable to access at least one of said encryption schemas in order to generate a length of string identifier, an encryption algorithm identifier, and a relative address code;

an address incrementing process executing on said processor, said address incrementing process responsive to said relative address code and operable to increment said address register variable,

whereby said encryption algorithm identifier identifies a particular encryption algorithm utilized to encrypt a set of data having a size defined by said length of string identifier.

17. A security apparatus as recited in claim 16 wherein at least one of said plurality of memories is a read-only memory, and wherein at least one of said memories is a writeable memory.

18. A security apparatus as recited in claim 17 further comprising an output port coupled to said processor, and an input port coupled to said output port.

19. A security apparatus as recited in claim 18 further comprising a downloading port separate from said input port for downloading encryption schema into said writeable memory.