Digital signal processor using a reconfigurable array of macrocells

• US 6,094,726 A
• Filed: 02/05/1998
• Issued: 07/25/2000
• Est. Priority Date: 02/05/1998
• Status: Expired due to Fees

• Current Assignee: George S. Sheng
• Original Assignee: George S. Sheng
• Inventors: Gonion, Jeffry E., Bilbrey, Brett C.
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US09/019,134
• Time in Patent Office: 901 Days
• Field of Search: 713/400, 713/401, 713/500, 713/501, 713/600, 714/734, 714/12, 714/724, 714/725, 714/731, 712/1, 712/10, 712/11, 712/201, 712/203, 712/221, 712/222, 712/223, 712/242, 365/233.5, 365/233, 360/77.04, 358/20, 327/144, 708/230, 708/236, 710/25, 710/118
• US Class Current: 713/400
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8046 Systolic arrays

Abstract

A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input data stream from an outside source or from other macrocells. The interconnects between each macrocell are arranged so that the function of the device is predetermined according to user specific applications.

Claims

1. A integrated circuit signal processing device comprising:

a nonvolatile memory means for storing a plurality of configuration parameters;

a processing means coupled to said nonvolatile memory means and consisting of;

means for equalizing incoming streams of data in time to create synchronized signals, said means comprising at least one input terminal for receiving said streams and at least one output terminal at which said synchronized signals are presented;

a set of interconnected arithmetic logic units communicably coupled to said output terminal for receiving said synchronized data; and

a set of configuration registers accessible by said arithmetic logic units, wherein the data in said configuration register determines the functionality of said interconnected logic units.

2. The device according to claim 1 wherein said means for equalizing automatically detects the difference in time between any two or more of said incoming streams of data.

3. The device according to claim 2 wherein said means of equalizing is further configured to automatically compensate for said difference in time between said two or more data signals.

4. The device according to claim 1 wherein said nonvolatile memory means contains a set of security bits that can selectively lock out access by a user to said configuration registers.

5. The device according to claim 1 wherein said non-volatile memory means comprise a set of mapping aliases which defines the addresses at which a user accesses each of said configuration parameters.

6. The device according to claim 4 wherein each of said configuration registers can be restricted on a bit wise basis.

7. The device according to claim 1 wherein each of said configuration registers are loaded with configuration parameters upon reset.

8. The device according to claim 1 wherein each of said configuration registers are loaded with configuration parameters upon power-up.

9. The device according to claim 3 wherein said means for equalizing may be configured as a set of equalization RAMs.

10. The device according to claim 3 wherein said means for equalizing may be configured as a set of FIFO'"'"'s.

11. The device according to claim 1 wherein said interconnected arithmetic logic units comprised of two adders and a multiplier used to perform a selective set of arithmetic operations on said synchronized signals.

12. A reconfigurable real time digital processing circuit comprising:

a plurality of interconnected macrocells, each of said macrocells comprising;

a means of equalizing incoming data streams received by the circuit; and

a plurality of arithmetic logic units coupled to said means of equalizing for receiving synchronized data therefrom;

a support block coupled to said plurality of interconnected macrocells, said support block providing interface between the processing circuit or and one or more external systems which deliver said incoming data streams;

an input block coupled to said plurality of interconnected macrocells for receiving digital data from and external source;

an output block coupled to said plurality of macrocells for transmitting processed information to at least one of said external systems.

13. The real time digital processor according to claim 12 wherein each of said plurality of interconnected macrocells further comprises a processing block used for equalizing said streams of incoming digital data.

14. The real time digital processor according to claim 12 wherein each of said plurality of interconnected macrocells comprises a universal set of memory registers used to control the operation of said macrocells.

15. The real time digital processor according to claim 12 wherein said macrocell comprises two adders and a multiplier configured to perform a selective set of arithmetic operations on incoming digital data.

16. The real time digital processor according to claim 12 wherein the outputs of macrocells are coupled to input of succeeding macrocells.

17. The real time digital processor according to claim 12 wherein said support block provides a means of generating a set of synchronization signals.

18. The real time digital processor according to claim 12 wherein said set of synchronization signals are used to equalize input signals entering said macrocells.

19. The real time digital processor according to claim 12 wherein said support block provides a means for calculating statistical data such as min, max, mean, etc., on said incoming stream.

20. The real time digital processor according to claim 12 wherein said support block provides a means for said external systems to read the contents of said control registers.

21. An integrated circuit for processing a plurality of multiple-bit data signals, comprising:

a plurality of input terminals for receiving respective ones of the data signals;

a plurality of output terminals;

a variable delay buffer coupled to the input terminals for receiving the data signals; and

logic circuitry coupled to the variable delay buffer for selectively delaying the data signals to equalize the data signals in time with respect to each other, thereby producing equalized data signals, the output terminals coupled to the variable delay buffer for presenting the equalized data signals.

22. The integrated circuit of claim 21, wherein the logic circuitry is capable of offsetting the data signals by a fixed amount in time.