Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof

• US 6,096,433 A
• Filed: 02/20/1998
• Issued: 08/01/2000
• Est. Priority Date: 02/20/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kikuchi, Hiroaki, Hamajima, Tomohiro
• Primary Examiner(s): Booth, Richard
• Application Number:
  US09/027,180
• Time in Patent Office: 893 Days
• Field of Search: 428/620, 428/446, 428/450, 438/455-459
• US Class Current: 428/446
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/12528 Semiconductor component

Abstract

An insulating layer is selectively grown on the major surface of a first silicon wafer, and is partially etched away so as to be retracted below the major surface; after the retraction of the insulating layer, the first silicon wafer is bonded to a second silicon wafer, and the major surface of the first silicon wafer is strongly adhered to the major surface of the second silicon wafer, so that the first silicon wafer is hardly separated from the second silicon wafer.

Claims

1. A semiconductor substrate used for a semiconductor device, comprising:

a first semiconductor substrate having a first major surface having a central area and a peripheral area surrounding said central area;

an insulating layer selectively formed in said first major surface, including a plurality of insulating sub-layers forming an insulating pattern in said peripheral area and having an upper surface retracted from said first major surface to form a recess therebetween, each of said plurality of insulating sub-layers being equal to or less than 1 mm² ; and

a second semiconductor substrate having a second major surface bonded to the central area of said first major surface and to the plurality of insulating sub-layers formed on the peripheral area of said first major surface.

2. The semiconductor substrate as set forth in claim 1, in which said upper surface is retracted from said first major surface by at least 0.1 micron.

3. The semiconductor substrate as set forth in claim 1, further comprising a protective layer covering a side surface of said first semiconductor substrate, a side surface of said second semiconductor substrate, and a back surface of said second semiconductor substrate.

4. A semiconductor substrate used for a semiconductor device, comprising:

a first semiconductor substrate having a first major surface having a central area and a peripheral area surrounding said central area, said peripheral area being water repellents;

an insulating layer selectively formed in said first major surface except said peripheral area and having an upper surface retracted from said first major surface to form a recess therebetween; and

a second semiconductor substrate having a second major surface bonded to said first major surface to cover said central area and said peripheral area, said second major surface having a water repellent peripheral area corresponding to said peripheral area.