Method for creating via hole in chip

• US 6,096,635 A
• Filed: 12/03/1997
• Issued: 08/01/2000
• Est. Priority Date: 10/21/1997
• Status: Expired due to Fees

• Current Assignee: Microjet Technology Co Limited (Microjet Technology)
• Original Assignee: Microjet Technology Co Limited (Microjet Technology)
• Inventors: Yang, Arnold Chang-Mou, Mou, Tse-Chi, Cheng, Shiang Ching, Chou, Chin-Yi
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US08/984,299
• Time in Patent Office: 972 Days
• Field of Search: 438/598, 438/618, 438/633, 438/637, 438/638, 438/667, 438/671, 438/689, 438/690, 438/691, 438/693, 438/706, 438/723, 438/743, 438/928, 438/959
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip or chips, and bombarding the chip(s) through the positioning holes on the transparent mask that correspond to the pre-formed pattern, with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existing IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-pattered mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.

Claims

1. A method for creating a via hole in a chip having thereon an integrated circuit structure on a first face thereof, comprising steps of:

determining a first position of a via hole to be created on said first face of said chip as desired;

determining a second position on a second face of said chip, wherein said second face is opposite to said first face, and said second position is aligned with said first position;

attaching a transparent mask having thereon a positioning hole to said second face, and having said positioning hole aligned with said second position; and

bombarding said chip through said positioning hole of said transparent mask with accelerated particles so as to create said via hole at said first position.

2. The method according to claim 1 wherein said transparent mask is made of a polymer material.

3. The method according to claim 2 wherein said polymer material is polyester.

4. The method according to claim 1 wherein said transparent mask is attached to said second face by gluing.

5. The method according to claim 1 wherein said positioning hole of said transparent mask is formed by a laser processing technique.

6. The method according to claim 1 wherein said step of determining said second position includes the sub-steps of:

attaching a transparent film onto said first face, wherein said transparent film has thereon a first positioning mark and a via hole pattern aligned with said first position;

providing a second positioning mark on said transparent mark, wherein said second positioning mark is aligned with said first positioning mark to have said positioning hole of said transparent mask located at said second position; and

releasing said transparent film.

7. The method according to claim 6 wherein said transparent film is larger than said chip, and said first positioning mark is located on said transparent film outside a chip area.

8. The method according to claim 7 wherein said transparent mask is larger than said chip, and said second positioning mark is located on said transparent mask outside said chip area.

9. The method according to claim 6 wherein said second positioning mark on said transparent mask is formed by a laser processing technique.

10. The method according to claim 6 wherein said transparent film is a camera film obtained by taking a picture for said integrated circuit structure of said chip.

11. The method according to claim 10 wherein said camera film is a positive film.

12. The method according to claim 11 wherein said via hole pattern on said transparent film is aligned with said first position by aligning said picture of said integrated circuit structure on said transparent film with said integrated circuit structure on said first face of said chip under the facilitation of a microscope.

13. The method according to claim 1 further comprising a step of providing a protective layer on said first face of said chip after determining said second position for protecting said integrated circuit structure of said chip from damage resulting from said accelerated particles.

14. The method according to claim 13 wherein said protective layer is a water-borne gelatinous material.

15. The method according to claim 14 wherein said water-borne gelatinous material is an image pro super adhesive.

16. The method according to claim 15 wherein said image pro super adhesive is coated on said first face and baked for 1˜

5 minutes under a temperature ranged between 80°

C. and about 120°

C. to form said protective layer.

17. The method according to claim 13 further comprising a step of providing an isolation layer on said protective layer to isolate said protective layer from the surrounding.

18. The method according to claim 17 wherein said isolation layer is made of paper.

19. The method according to claim 1 wherein said accelerated particles are sand grains projected from a sand blower.