Semiconductor logic element and apparatus using thereof

• US 6,097,036 A
• Filed: 09/08/1997
• Issued: 08/01/2000
• Est. Priority Date: 03/08/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamaguchi, Ken, Teshima, Tatsuya, Mizuta, Hiroshi
• Primary Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/913,189
• Time in Patent Office: 1,058 Days
• Field of Search: 257/26-27, 257/8-9, 257/29, 257/192, 257/194, 257/12, 326/37-38, 326/54, 326/135
• US Class Current: 257/26
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors
• CPC Class Codes: H01L 29/7606 Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12

Abstract

A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.

Claims

1. A semiconductor logic element having a semiconductor substrate with an output electrode for issuing a high or low level voltage when a high or low level voltage is applied respectively to the first, second, third and fourth control electrodes, wherein:

said first and third control electrodes are disposed adjacent to each other,

said second control electrode is formed adjacent to said first and third control electrodes,

said fourth control electrode is formed adjacent to said first and third control electrodes, and opposite the second control electrode relative to said first and third control electrodes, and

said output electrode issues a voltage based on a first logic operation in response to a voltage applied to said first and second control electrodes, while a fixed low level voltage is applied to said second and fourth control electrodes, and said output electrode issues a voltage based on a second logic operation and differing from the first logic operation in response to a voltage applied to said first and third control electrodes, while a fixed high level voltage is applied to said second and fourth control electrodes.

2. A semiconductor logic element according to claim 1 wherein the first logic operation is a NOR logic operation and the second is an OR logic operation.

3. A semiconductor logic element having a semiconductor substrate with one output electrode for issuing a high or low level voltage when a high or low level voltage is applied respectively to first, second, third and fourth control electrodes wherein:

said first and third control electrodes are formed adjacent to each other,

said second control electrode is formed adjacent to said first and third control electrodes,

said fourth control electrode is formed adjacent to said first and third control electrodes, and opposite the second control electrode relative to said first and third control electrodes, and

said output electrode issues a voltage based on an AND logic operation in response to a voltage applied to said second and fourth control electrodes, while a fixed low level voltage is applied to said first and third control electrodes.

4. A semiconductor logic element having a semiconductor substrate with one output electrode for issuing a high or low level voltage when a high or low level voltage is applied respectively to first, second, third and fourth control electrodes, wherein:

said first and third control electrodes are formed adjacent to each other,

said second control electrode is formed adjacent to said first and third control electrodes,

said fourth control electrode is formed adjacent to said first and third control electrodes, and opposite the second control electrode relative to said first and third control electrodes, and

said output electrode issues a voltage based on an EXNOR logic operation in response to a voltage applied to said first and second control electrodes, while a fixed low level voltage is applied to said third and fourth control electrodes.

5. A semiconductor logic element having a semiconductor substrate with one output electrode for issuing a high or low level voltage when a high or low level voltage is applied respectively to at least first, second and third control electrodes electrically connected to said semiconductor substrate, wherein:

said semiconductor logic element has a first channel located within said semiconductor substrate between said first and said second control electrodes and carriers move in said first channel towards said output electrode,

said semiconductor logic element has a second channel located within said semiconductor substrate between said first and said third control electrodes and carriers do not move substantially in said second channel towards said output electrode, and

said output electrode issues a voltage in response to a plurality of logic operations resulting from applications of a voltage to said first, second and third control electrodes.

6. A semiconductor logic element comprising:

a collector layer made from a first semiconductor piece having a first band gap,

a barrier layer formed on said collector layer, said barrier layer being made from a second semiconductor piece and having a second band gap wider than said first band gap,

a channel layer formed from a third semiconductor piece on said barrier layer and having a third band gap narrower than said second band gap,

a carrier supply layer formed in said channel layer for supplying carriers to said channel layer made from a fourth semiconductor having a fourth band gap wider than said third band gap, and

at least first, second and third control electrodes electrically connected to said channel layer, and having one output electrode electrically connected to said collector layer, wherein;

a first channel is formed between said first and second control electrodes, and carriers moving between said control electrodes make a real space transition of said barrier and move towards said collector layer, and

a second channel is formed between said first and third control electrodes, and carriers moving between said control electrodes make a real space transition of said barrier and move towards said collector layer and the quantity of carriers transiting said second channel and moving to said collector layer is smaller than the quantity of carriers transiting said first channel and moving to said collector layer.

7. A semiconductor logic element comprising:

a substrate, and a carrier supply layer formed on said substrate of a first semiconductor piece, and having a first band gap for supplying carriers to a channel layer wherein the channel layer is made from a second semiconductor piece formed on said substrate, said channel layer having a second band gap narrower than said first band gap,

a barrier layer made from a third semiconductor piece formed on said substrate and having a third band gap wider than said second band gap,

a collector layer made from a fourth semiconductor piece formed on said barrier layer and having a fourth band gap narrower than said third band gap,

at least first, second and third control electrodes electrically connected to said channel layer, and

an output electrode electrically connected to said collector layer, wherein;

a first channel is formed between said first and second control electrodes, and carriers moving between said control electrodes make a real space transition of said barrier and move towards said collector layer, and

a second channel is formed between said first and third control electrodes, and carriers moving between said control electrodes make a real space transition of said barrier and move towards said collector layer, and the quantity of carriers transiting said second channel and moving to said collector layer is smaller than the quantity of carriers transiting said first channel and moving to said collector layer.

8. A semiconductor logic element comprising:

a collector layer made from a first semiconductor piece having a first band gap,

a barrier layer made from a second semiconductor piece formed on said collector layer and having a second band gap wider than said first band gap,

a channel layer made from a third semiconductor piece formed on said barrier layer and having a third band gap narrower than said second band gap,

a carrier supply layer formed on said channel layer made from said fourth semiconductor piece, and having a fourth band gap wider than a third band gap for supplying carriers to said channel layer,

having at least first, second and third control electrodes electrically connected to said channel layer, and

having one output electrode electrically connected to said collector layer,

a first channel formed between said first and second control electrodes, having a first channel length, and

a second channel formed between said first and third control electrodes, said second channel having a channel length shorter than said first channel length.

9. A semiconductor logic element according to claim 8 wherein said first channel length is equal to or greater than the ballistic transport distance R_b of the carrier within said channel layer and said second channel length is less than R_b.

10. A semiconductor logic element comprising:

a substrate,

a carrier supply layer formed on said substrate of said first semiconductor piece, and having a first band gap for supplying carriers to a channel layers, wherein the channel layer is made from a second semiconductor piece formed on said substrate and having a second band gap narrower than said first band gap,

a barrier layer made from a third semiconductor piece formed on said substrate and having a third band gap wider than said second band gap,

a collector layer made from a fourth semiconductor piece formed on said barrier layer and having a fourth band gap narrower than said third band gap,

at least first, second and third control electrodes electrically connected to said channel layer, and an output electrode electrically connected to said collector layer,

a first channel formed between said first and second control electrodes, having a first channel length, and

a second channel formed between said first and third control electrodes, said second channel having a channel length shorter than said first channel length.

11. A semiconductor logic element according to claim 10 wherein said first channel length is equal to or greater than the ballistic transport distance R_b of the carrier within said channel layer and said second channel length is less than R_b.

12. A semiconductor logic element comprising:

a collection layer made from a first semiconductor piece having a first band gap,

a barrier layer made from a second semiconductor piece formed on said collector layer and having a second band gap wider than said first band gap,

a channel layer made from a third semiconductor piece formed on said barrier layer and having a third band gap narrower than said second band gap,

a carrier supply layer formed on said channel layer made from a fourth semiconductor piece, and having a fourth band gap wider than a third band gap for supplying carriers to said channel layer,

at least first, second and third control electrodes electrically connected to said channel layer, and having one output electrode electrically connected to said collector layer,

a first channel between said first and said second control electrodes, having an impurity concentration, and a second channel of semiconductor having a lower impurity concentration than said first channel, said second channel being formed between said first and said third control electrodes.

13. A semiconductor logic element comprising:

a substrate,

a carrier supply layer formed from said substrate of a first semiconductor piece, and having a first band gap for supplying carriers to a channel layer, wherein the channel layer is made from a second semiconductor piece formed on said carrier supply layer and having a second band gap narrower than said first band gap,

a barrier layer made from a third semiconductor piece formed on said channel layer and having a third band gap wider than said second band gap,

a collector layer made from a fourth semiconductor piece formed on said barrier layer and having a fourth band gap narrower than said third band gap,

at least first, second and third control electrodes electrically connected to said channel layer, and an output electrode electrically connected to said collector layer,

a first channel between said first and said second control electrodes, having a first impurity concentration, and

a second channel of semiconductor having a second impurity concentration lower than said first impurity concentration, said second channel being formed between said first and said third control electrodes.

14. A microprocessor utilizing a semiconductor logic element, comprising:

a semiconductor substrate,

at least first, second and third control electrodes for applying a high or a low level voltages respectively,

an output electrode for output of a high or a low level voltage in response to applied voltage to said at least first, second, and third control electrodes, respectively, said output electrode outputting a voltage level along with one or more logic operations resulting from applying a voltage to said first, second and third control electrodes, respectively,

a tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively,

a non-tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively, and

a controller for controlling an arithmetic unit, register and decoder also contained in said microprocessor,

wherein at least one of first, second or third control electrodes for said arithmetic unit, register and decoder are input, respectively, with a high or a low level voltage, wherein the substrate has an output electrode for issuing a high or a low level voltage according to the voltage applied to said first, second and third control electrodes, and wherein said output electrode issues a voltage at a level based on a plurality of logic operations performed in response to voltage applied to the respective control electrodes.

15. A computer utilizing a semiconductor logic element comprising:

a semiconductor substrate,

at least first, second and third control electrodes for applying a high or a low level voltage, respectively,

an output electrode for output of a high or a low level voltage in response to applied voltage to said at least first, second, and third control electrodes, respectively, said output electrode outputting a voltage level along with one or more logic operations resulting from applying a voltage to said first, second and third control electrodes, respectively,

a tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltages respectively,

a non-tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively,

a microprocessor including a controller for controlling an arithmetic unit, register and decoder contained in said microprocessor, and

a main memory, an interface including a graphical accelerator, and a computer with paths for connecting said interface with said microprocessor and said main memory, wherein at least one of first, second or third control electrodes for said microprocessor, main memory and interface are input respectively with a high or a low level voltage, wherein said substrate has an output electrode for issuing a high or a low level voltage according to the voltage applied to said first, second and third control electrodes, and said output electrode issues a voltage at a level based on a plurality of logic operations performed in response to voltage applied to the respective control electrodes.

16. A semiconductor logic element comprising:

a collector layer made of a first semiconductor region having a first band gap,

a barrier layer made of a second semiconductor region having a second band gap wider than said first band gap, formed on said collector layer,

a channel layer made of a third semiconductor region having a third band gap narrower than said second band gap,

a carrier supply layer made of a fourth semiconductor region having a fourth band gap wider than a third band gap for supplying carriers to said channel layer, formed on said channel layer,

at least a first, a second, and a third control electrode electrically connected to said channel layer,

an output electrode electrically connected to said collector layer,

a first channel of semiconductor having a first electronegativity, formed between said first and second control electrodes, and

a second channel of semiconductor having a second electronegativity larger than the first electronegativity, formed between said first and third control electrodes.

17. A semiconductor logic element comprising:

a substrate,

a carrier supply layer made of a first semiconductor region having a first band gap for supplying carriers to a channel layer, formed on said substrate,

a channel layer made of a second semiconductor region having a second band gap, narrower, than said first band gap, formed on said carrier supply layer,

a barrier layer made of a third semiconductor region having a third band gap wider than said second band gap, formed on said channel layer,

a collector layer made of a fourth semiconductor region having a fourth band gap narrower than said third band gap, formed on said barrier layer,

at least a first, a second, and a third control electrode electrically connected to said channel layer,

an output electrode electrically connected to said collector layer,

a first channel of semiconductor having a first electronegativity, formed between said first and second control electrodes, and

a second channel of semiconductor having a second electronegativity larger than the first electronegativity, formed between said first and third control electrodes.

18. A semiconductor logic element comprising:

a semiconductor substrate,

at least first, second and third control electrodes for applying a high or a low level voltage, respectively,

an output electrode for output of a high or a low level voltage in response to applied voltage to said at least first, second, and third control electrodes, respectively, said output electrode outputting a voltage level along with one or more logic operations resulting from applying a voltage to said first, second and third control electrodes, respectively,

a tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively, and

a non-tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively.

19. A semiconductor logic element according to claim 18 utilized in a full adder.

20. A semiconductor logic element according to claim 18 utilized in an arithmetic unit.

21. A semiconductor logic element according to claim 18 utilized in a register.

22. A semiconductor logic element according to claim 18 utilized in a decoder.

23. A semiconductor logic element according to claim 18 utilized in a memory.

24. A semiconductor logic element according to claim 18 utilized in a graphic accelerator.

25. A semiconductor logic element comprising:

a semiconductor substrate,

at least first, second, and third control electrodes for applying a high or a low level voltage, respectively,

an output electro de for output of a high or a low level voltage in response to applied voltage to said at least first, second, and third control electrodes, respectively, said output electrode outputting a voltage level along with one or more logic operations resulting from applying a voltage to said first, second and third control electrodes, respectively,

a tunneling channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively, and

a non-tunneling channel between one control electrode and another control electrode selected from th e group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively,

wherein said output electrode outputs a voltage at a level in response to a first logic operation resulting from applying a voltage to said first and third control electrode in case of applying a fixed low voltage to said second electrode, and said output electrode outputs a voltage at a level in response to a second logic operation differing from the first logic operation and resulting from applying a voltage to said first and third control electrode in case of applying a fixed high voltage to said second electrode.

26. A semiconductor logic element comprising:

a semiconductor substrate,

at least first, second, and third control electrodes for applying a high or a low level voltage, respectively,

an output electrode for output of a high or a low level voltage in response to applied voltage to said at least first, second, and third control electrodes, respectively, said output electrode outputting a voltage level along with one or more logic operations resulting from applying a voltage to said first, second and third control electrodes, respectively,

a first channel having a lower tunneling rate than a second channel between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltages respectively, and

a second channel having a higher tunneling rate than the first channel, the second channel being formed between one control electrode and another control electrode selected from the group of said at least first, second, and third control electrodes for applying a high or a low level voltage, respectively.