Vertical field effect transistor and diode

• US 6,097,046 A
• Filed: 11/29/1993
• Issued: 08/01/2000
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Plumton, Donald L.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/158,673
• Time in Patent Office: 2,437 Days
• Field of Search: 257/266, 257/583, 257/270, 257/272, 257/471, 257/472, 257/476, 257/474, 257/267
• US Class Current: 257/266
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Claims

1. An integrated circuit, comprising:

(a) a vertical field effect transistor with parallel buried gate fingers and with a drain in a first portion of a first layer of semiconductor material; and

(b) a diode with a cathode including a second portion of said first layer and spaced from said first portion;

(c) wherein (i) said first layer includes a portion of a GaAs substrate doped n type to a first concentration and an epilayer of GaAs doped to a second concentration which is less than said first concentration, (ii) said gate fingers are p type GaAs on said epilayer with n type GaAs channels on said epilayer between adjacent ones of said gate fingers, (iii) a source layer of n type GaAs is on said gate fingers and channels, (iv) said cathode includes a portion of said epilayer and said substrate, and (v) a trench in said epilayer separates said transistor and said diode.

2. An integrated circuit, comprising:

(a) a vertical field effect transistor with parallel buried gate fingers and with a drain in a first portion of a first layer of semiconductor material; and

(b) a diode with a cathode including a second portion of said first layer and spaced from said first portion;

(c) wherein (i) said first layer includes a portion of a GaAs substrate doped n type to a first concentration and an epilayer of GaAs doped to a second concentration which is less than said first concentration, (ii) said gate fingers are p type GaAs on said epilayer with n type GaAs channels on said epilayer between adjacent ones of said gate fingers, (iii) a source layer of n type GaAs is on said gate fingers and channels, (iv) said cathode includes a portion of said epilayer and said substrate, and (v) said cathode includes a portion of said source layer spaced from said gate fingers and channels.

3. An integrated circuit, comprising:

(a) a vertical field effect transistor with parallel buried gate fingers and with a drain in a first portion of a first layer of semiconductor material; and

(b) a diode with a cathode including a second portion of said first layer and spaced from said first portion;

(c) wherein (i) said first layer includes a portion of a GaAs substrate doped n type to a first concentration and an epilayer of GaAs doped to a second concentration which is less than said first concentration, (ii) said gate fingers are p type GaAs on said epilayer with n type GaAs channels on said epilayer between adjacent ones of said gate fingers, (iii) a source layer of n type GaAs is on said gate fingers and channels, (iv) said cathode includes a portion of said epilayer and said substrate, and (v) a p type region extending from a surface of said source layer to said gate fingers and wherein said diode includes a p type anode with doping profile the same as that of said p type region.