Semiconductor device having a plurality of parallel drift regions

• US 6,097,063 A
• Filed: 01/21/1997
• Issued: 08/01/2000
• Est. Priority Date: 01/22/1996
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujihira, Tatsuhiko
• Primary Examiner(s): Guay, John
• Application Number:
  US08/786,473
• Time in Patent Office: 1,288 Days
• Field of Search: 257/139, 257/141, 257/266, 257/287, 257/339, 257/341-343, 257/347, 257/401, 257/409, 257/493, 257/653, 257/654
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1012 Base regions of thyristors H01L29/083 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Claims

1. A semiconductor device comprising a drift region, said drift region having a drift current flowing if said drift region is in an ON mode, said drift region being depleted if said drift region is in an OFF mode, said drift region being formed as a structure comprising

a plurality of first conductivity type drift path regions connected together in parallel to form a group of parallel drift paths,

a plurality of second conductivity type compartment regions, each of said second conductivity type compartment regions being positioned between adjacent said first conductivity type drift path regions to thereby form p-n junctions therebetween,

a first additional second conductivity type side region connected to an outer side of a first conductivity type drift path region positioned at a first outer side of said group of parallel drift paths, wherein said first additional second conductivity type side region has substantially the same length and thickness as that of said second conductivity type compartment regions, and

a second additional second conductivity type side region connected to an outer side of a first conductivity type drift path region positioned at a second outer side of said group of parallel drift paths, wherein said second additional second conductivity type side region has substantially the same length and thickness as that of said second conductivity type compartment regions.

2. A semiconductor device comprising a drift region, said drift region having a drift current flowing if said drift region is in an ON mode, said drift region being depleted if said drift region is in an OFF mode, said drift current flowing in a lateral direction, said drift region being formed on a semiconductor or an insulation film on said semiconductor,

said drift region being formed as a parallel stacked structure comprising a plurality of layer-shaped first conductivity type drift path regions and a plurality of layer-shaped second conductivity type compartment regions alternately stacked on a plane in parallel and adjacent to one another,

said semiconductor further comprising a first additional second conductivity type side region connected to an outer side of a first conductivity type drift path region positioned at a first outer side of said parallel stacked structure, wherein said first additional second conductivity type side region has substantially the same length and thickness as that of said second conductivity type compartment regions,

said semiconductor further comprising a second additional second conductivity type side region connected to an outer side of a first conductivity type drift path region positioned at a second outer side of said parallel stacked structure, wherein said second additional second conductivity type side region has substantially the same length and thickness as that of said second conductivity type compartment regions.