Electro-static discharge protection structure for semiconductor devices

• US 6,097,066 A
• Filed: 10/06/1997
• Issued: 08/01/2000
• Est. Priority Date: 10/06/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Shih, Jiaw-Ren, Wu, Yi-Hsun
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US08/944,823
• Time in Patent Office: 1,030 Days
• Field of Search: 257/546, 257/355, 257/360, 257/356, 257/357
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

The structure includes a plurality of first ring shape structure formed on a semiconductor wafer to act as the gates of the MOS devices. The areas in the inner side of the first ring shape structures are drain regions. A plurality of source regions having second ring shape structures are formed around each sides the first ring shape structures. A p conductive type region is formed in the wafer adjacent to the source regions. A third ring shape structure is formed in the semiconductor wafer to surround the p+conductive type region for serving as a guard ring.

Claims

1. An electro-static discharge (ESD) protection structure for semiconductor devices, said structure comprising:

a plurality of first ring-shaped gate structures formed on a semiconductor wafer;

a plurality of first doped regions formed in said wafer in inner areas of said first ring shape structures to act as drains, said plurality of first doped regions including n conductive type ions;

a plurality of second doped regions formed in said wafer, said plurality of second doped regions being second ring shape structures;

wherein each of said plurality of second doped regions surrounds only one of said plurality of gate structures; and

wherein said plurality of second doped regions includes n conductive type ions to serve as sources;

a p conductive type ions region formed around said plurality of second doped regions and between thereof, thereby separating said plurality of second doped regions; and

a third ring shape structure having n conductive type ions surrounding said p conductive type ions region and being separated from said p conductive type ions region with a space to act as a guard ring.

2. The structure of claim 1, wherein said plurality of first doped regions are drains of said semiconductor devices.

3. The structure of claim 2, wherein said plurality of second doped regions are sources of said semiconductor devices.

4. The structure of claim 1, wherein said second conductive type ions region is electrically connected to ground during operation.

5. The structure of claim 1, wherein said third ring shape structure is electrically connected to Vcc during operation.

6. The structure of claim 1, wherein said plurality of first ring shape structures are selected from a group consisting of square ring shapes and rectangular ring shapes.

7. The structure of claim 1, wherein said plurality of second ring shape structures are selected from a group consisting of square ring shapes and rectangular ring shapes.

8. The structure of claim 1, wherein said third ring shape structure is selected from the group consisting of a square ring shape and a rectangular ring shape.

9. A structure of NMOS devices formed in a semiconductor wafer, said structure comprising:

at least two pairs of gates formed over said semiconductor wafer, each pair of said gates being spaced from each other;

drains, including n-conductive ions, formed in said semiconductor wafer in areas between two said gates of a same pair;

sources, including n-conductive ions, formed in said semiconductor wafer adjacent to said gates separated from said drains, at least two of said sources formed in said space;

first p conductive type ion regions formed in said semiconductor wafer being adjacent to said sources that are not in said space;

a second p conductive type ion region formed in said semiconductor wafer being between and adjacent to said sources that are in said space, wherein said first p conductive type ion regions and said second p conductive type ion regions formed between said at least two pair of gates provide for a uniform current distribution; and

first conductive ion regions formed in a peripheral area of said first p conductive type ions regions and kept a distance from said first p conductive type ions regions to act as a guard ring.